公开(公告)号：US20160170115A1

公开(公告)日：2016-06-16

申请号：US14681952

申请日：2015-04-08

Applicant: Samsung Display Co. Ltd.

Inventor： Tae Woo KIM ,  Min Hyuck KANG ,  Eun Ae KWAK ,  Moon Gyu LEE ,  Hyeong Gyu JANG

IPC: G02B5/30 ,  H01J37/32

CPC classification number: G02B5/3058

Abstract: A method of manufacturing a wire grid polarizer is provided. The method includes: forming an electrical conductive layer on a substrate; forming a guide pattern layer on the electrical conductive layer, wherein the guide pattern layer includes two or more linear structures separated from one another; forming a fluorocarbon surface modification layer on each of the linear structures using a fluorine-based gas plasma treatment; and forming a neutral layer on the electrical conductive layer, wherein the neutral layer has a nonselective affinity with repeating units of a block copolymer.

Abstract translation: 提供一种线栅偏振器的制造方法。 该方法包括：在基板上形成导电层; 在所述导电层上形成引导图案层，其中所述引导图案层包括彼此分离的两个或更多个线性结构; 使用氟基气体等离子体处理在每个线性结构上形成氟碳表面改性层; 以及在所述导电层上形成中性层，其中所述中性层与嵌段共聚物的重复单元具有非选择性亲和力。

公开(公告)号：US20160131811A1

公开(公告)日：2016-05-12

申请号：US14668617

申请日：2015-03-25

Applicant: Samsung Display Co. Ltd.

Inventor： Su Mi LEE ,  Min Hyuck KANG

IPC: G02B5/30

CPC classification number: G02B5/3058 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0005

Abstract: Provided is a method of fabricating a wire grid polarizer, the method comprising an organic light-emitting display panel. According to an aspect of the present disclosure, there is provided a method comprising sequentially stacking a conductive wire pattern layer, a first neutral layer, a guide pattern layer and a second neutral layer on a substrate, forming etch-stop patterns on the second neutral layer, forming second neutral layer patterns and guide patterns by patterning the second neutral layer and the guide pattern layer using the etch-stop patterns, coating a block copolymer of two types of monomer blocks having different etch rates on the first neutral layer and the second neutral layer patterns, aligning the block copolymer, removing one type of monomer blocks from the aligned block copolymer, and patterning the conductive wire pattern layer using the remaining monomer blocks, the second neutral layer patterns, and the guide patterns.

Abstract translation: 提供一种制造线栅偏振器的方法，该方法包括有机发光显示面板。 根据本公开的一个方面，提供了一种方法，包括在衬底上顺序堆叠导线图案层，第一中性层，引导图案层和第二中性层，在第二中性线上形成蚀刻停止图案 层，通过使用蚀刻停止图案图案化第二中性层和引导图案层来形成第二中性层图案和引导图案，在第一中性层上涂覆具有不同蚀刻速率的两种类型的单体嵌段的嵌段共聚物，第二中性层 中和层图案，对准嵌段共聚物，从对准的嵌段共聚物中除去一种类型的单体嵌段，以及使用剩余的单体嵌段，第二中性层图案和导向图案来图案化导电丝图案层。

公开(公告)号：US20160077263A1

公开(公告)日：2016-03-17

申请号：US14623708

申请日：2015-02-17

Applicant: Samsung Display Co., Ltd.

Inventor： Eun Ae KWAK ,  Min Hyuck KANG ,  Moon Gyu LEE

IPC: G02B5/30 ,  G02F1/1335

CPC classification number: G02B5/3058 ,  B81C1/00388 ,  B81C1/00404 ,  B81C2201/0149 ,  C09K13/00 ,  C23F4/00 ,  G02F2001/133548 ,  G03F7/0041 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method of fabricating a wire grid polarizer includes sequentially depositing a conductive wire pattern layer, and a plurality of guide patterns which forms one or more trenches therebetween on the conductive wire pattern layer, hydrophobically treating surfaces of the conductive wire pattern layer exposed in the trenches, and the guide patterns, coating the hydrophobically treated conductive wire pattern layer in the trenches with a neutral layer to partially fill the trenches, filling a remainder of the trenches with a block copolymer of two monomers with different etching rates, aligning the block copolymer filled in the trenches, selectively removing blocks of one monomer among the two monomers from the aligned block copolymer, and patterning the conductive wire pattern layer by using blocks of the other monomer among the two monomers remaining in the trenches and the guide patterns as a mask.

Abstract translation: 制造线栅偏振器的方法包括依次沉积导线图案层和在导线图案层上形成一个或多个沟槽的多个引导图案，疏水处理暴露在沟槽中的导线图案层的表面 和引导图案，用中性层在沟槽中涂覆疏水处理的导线图案层以部分地填充沟槽，用不同蚀刻速率的两种单体的嵌段共聚物填充剩余的沟槽，使嵌段共聚物填充 在沟槽中，选择性地从对准的嵌段共聚物中除去两种单体中的一种单体的嵌段，并且通过使用留在沟槽中的两种单体中的其它单体的嵌段和导向图案作为掩模来对导电丝图案图案化。