公开(公告)号：US20230238394A1

公开(公告)日：2023-07-27

申请号：US18158421

申请日：2023-01-23

Applicant: Samsung Display Co., LTD.

Inventor： Kye Uk LEE ,  Nak Cho CHOI ,  Sang Woo AN ,  Yong Duck SON ,  Won Ho JANG ,  Jung Hwan HWANG ,  Myung Koo HUR

IPC: H01L27/12 ,  H01L25/16

CPC classification number: H01L27/124 ,  H01L25/167 ,  H01L27/1218 ,  H01L24/05

Abstract: A display device includes a substrate including a first surface, a second surface opposite to the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a side surface connecting the first chamfered surface to the second chamfered surface, a pixel on the first surface of the substrate and including a light emitting element to emit light, a plurality of front pad parts on an edge of the first surface of the substrate and electrically connected to the pixel, a plurality of rear pad parts on an edge of the second surface of the substrate, and a plurality of side surface connection lines on the side surface of the substrate electrically connecting the plurality of front pad parts to the plurality of rear pad parts.

公开(公告)号：US20230237937A1

公开(公告)日：2023-07-27

申请号：US17890937

申请日：2022-08-18

Applicant: Samsung Display Co., LTD.

Inventor： Nak Cho CHOI ,  Sang Woo AN ,  Yong Duck SON ,  Won Ho JANG ,  Myung Koo HUR

IPC: G09F9/302 ,  H01L33/62 ,  H01L25/075 ,  H01L33/44 ,  H01L33/38

CPC classification number: G09F9/3026 ,  H01L33/62 ,  H01L25/0753 ,  H01L33/44 ,  H01L33/382

Abstract: A display device includes: a substrate; a transistor layer on a first surface of the substrate; a pad portion; a first via layer on the transistor layer, and spaced from the pad portion; a second via layer on the first via layer, and exposing an upper surface of the first via layer; a third via layer on the second via layer, and exposing an upper surface of the second via layer; a display element layer on the third via layer; a lead line on a second surface of the substrate; a side surface connection line on the first surface, the second surface, and a side surface between the first surface and the second surface, the side surface connection line electrically connecting the pad portion to the lead line; and an over-coating layer covering the side surface connection line, and overlapping with the exposed upper surface of the first via layer.