公开(公告)号：US20240331642A1

公开(公告)日：2024-10-03

申请号：US18604293

申请日：2024-03-13

Applicant: Samsung Display Co., Ltd.

Inventor： SANG YONG NO ,  SUNKWUN SON ,  DONG HEE SHIN

IPC: G09G3/3266 ,  G06F3/042 ,  G09G3/32 ,  H10K59/40

CPC classification number: G09G3/3266 ,  G06F3/0421 ,  G09G3/32 ,  H10K59/40 ,  G09G2310/0267 ,  G09G2310/08

Abstract: Disclosed is a sensor of a display device including a light-sensing element connected to a first sensing node, a first transistor connected between a reset voltage line and the first sensing node, a second transistor connected between a sensor-driving voltage line and a second sensing node, and including a gate electrode connected to the first sensing node, a third transistor connected between the second sensing node and a readout line, and including a gate electrode connected to a scan line, and a compensation capacitor connected between the gate electrode of the second transistor and the scan line.

公开(公告)号：US20240331612A1

公开(公告)日：2024-10-03

申请号：US18395528

申请日：2023-12-23

Applicant: Samsung Display Co., LTD.

Inventor： SANG YONG NO ,  KYUNGHO KIM ,  GICHANG LEE

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2340/0435

Abstract: A display panel includes a first display region to an N-th display region disposed in a row direction. A P-th display region includes a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor which receives an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, where the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal, and a P-th region control circuit including a first control transistor which outputs a high gate voltage of the compensation gate signal, and a second control transistor which outputs a low gate voltage of the compensation gate signal, where the first control transistor and the second control transistor are controlled based on a P-th region control signal.

公开(公告)号：US20240312391A1

公开(公告)日：2024-09-19

申请号：US18519808

申请日：2023-11-27

Applicant: Samsung Display Co., LTD.

Inventor： KYUNGHO KIM ,  SANG YONG NO ,  GICHANG LEE

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/061 ,  G09G2310/08

Abstract: A gate driving circuit includes: a first pull up control circuit for controlling a voltage of a pull up control node in response to a previous carry signal; a pull down control circuit for controlling a voltage of a pull down control node in response to the voltage of the pull up control node; a boosting circuit including a boosting capacitor and for boosting the voltage of the pull up control node; a gate output circuit for outputting a plurality of gate signals having different timings in response to the voltage of the pull up control node and the voltage of the pull down control node; and a stabilizing circuit including a control electrode connected to an end of the boosting capacitor, a first electrode for receiving a first high power voltage and a second electrode connected to the first pull up control circuit.

公开(公告)号：US20240078958A1

公开(公告)日：2024-03-07

申请号：US18447859

申请日：2023-08-10

Applicant: Samsung Display Co., LTD.

Inventor： SANG YONG NO

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2300/0426 ,  G09G2310/08

Abstract: A gate driving circuit includes: a pull-up control circuit configured to control a voltage of a pull-up control node in response to a pull-up control signal; a pull-down control circuit configured to control a voltage of a pull-down control node in response to the voltage of the pull-up control node; a carry output circuit configured to output a carry signal in response to the voltage of the pull-up control node and the voltage of the pull-down control node; and a gate output circuit configured to output a plurality of gate signals having different timings in response to the voltage of the pull-up control node and the voltage of the pull-down control node, wherein a width of the carry signal is greater than a width of each of the gate signals.