公开(公告)号：US11789168B2

公开(公告)日：2023-10-17

申请号：US17408679

申请日：2021-08-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gilles Gasiot ,  Fady Abouzeid

IPC: G01T1/24 ,  H01L27/07 ,  H01L31/103

CPC classification number: G01T1/248 ,  G01T1/247 ,  H01L27/0761 ,  H01L31/103

Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

公开(公告)号：US10469058B1

公开(公告)日：2019-11-05

申请号：US15990944

申请日：2018-05-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Guenole Lallement ,  Fady Abouzeid

IPC: H03K3/013 ,  H03K3/012 ,  H03K3/03

Abstract: A multi-stage ring oscillator generates an output clock signal having a frequency which is dependent on a digitally leakage current that is applied to each stage of the multi-stage ring oscillator. A magnitude of a leakage current sourced by each digitally controlled leakage current source is set by a control circuit in response to a selection signal. A calibration circuit processes a reference clock signal and the output clock signal generated by the multi-stage ring oscillator to make adjustment to the selection signal which drives a locking of a frequency of the output clock signal to a desired frequency.

公开(公告)号：US10090827B2

公开(公告)日：2018-10-02

申请号：US15414419

申请日：2017-01-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrik Temleitner ,  Fady Abouzeid

IPC: H03K3/356 ,  H03K19/21

Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

公开(公告)号：US10739807B2

公开(公告)日：2020-08-11

申请号：US16127771

申请日：2018-09-11

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Guenole Lallement ,  Fady Abouzeid

IPC: G05F3/20 ,  H03K19/0948 ,  H01L29/78 ,  H01L27/092 ,  H03K19/00 ,  G06F30/30

Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.

公开(公告)号：US20180062652A1

公开(公告)日：2018-03-01

申请号：US15443779

申请日：2017-02-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fady Abouzeid ,  Gilles Gasiot

IPC: H03K19/003 ,  H03K3/356

Abstract: A storage element including two CMOS inverters, coupled head-to-tail between two nodes; and one MOS transistor, connected as a capacitor between said nodes.