公开(公告)号：US20130154067A1

公开(公告)日：2013-06-20

申请号：US13765594

申请日：2013-02-12

Applicant: Stats ChipPac, Ltd.

Inventor： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

IPC: H01L23/495

CPC classification number: H01L23/4952 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.

Abstract translation: 半导体器件具有垂直偏移的BOT互连结构。 垂直偏移通过引线框架实现，引线框架具有围绕模板的多个引线。 在引线指上形成第一导电层。 在引线指上形成第二导电层。 每个第二导电层定位成与第一导电层相邻，并且每个第一导电层定位成与第二导电层相邻。 第二导电层的高度大于第一导电层的高度。 第一和第二导电层可以具有并排布置或交错布置。 在第一和第二导电层上形成凸起。 接合线电连接到凸块。 半导体管芯安装在引线框架的管芯上并电连接到接合线和BOT互连结构。