公开(公告)号：US20200241958A1

公开(公告)日：2020-07-30

申请号：US16683989

申请日：2019-11-14

Applicant: SK hynix Inc.

Inventor： Won-Gyu SHIN

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/09 ,  G06F12/02

Abstract: A memory system includes: a first error detection circuit suitable for generating a first error detection code using host data and a host address which are transferred from a host; a second error detection circuit suitable for generating a second error detection code using system data including one or more host data, a logical address corresponding to one or more host addresses, a physical address corresponding to the logical address and one or more first error detection codes; a third error detection code suitable for generating a third error detection code using the system data, the one or more first error detection codes and the second error detection code; and a first memory suitable for storing the system data, the one or more first error detection codes, the second error detection code and the third error detection code.

公开(公告)号：US20190188077A1

公开(公告)日：2019-06-20

申请号：US16038792

申请日：2018-07-18

Applicant: SK hynix Inc.

Inventor： Jung-Hyun KWON ,  Do-Sun HONG ,  Seung-Gyu JEONG ,  Won-Gyu SHIN

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52

CPC classification number: G06F11/1072 ,  G06F11/1056 ,  G06F2201/81 ,  G11C29/42 ,  G11C29/52

Abstract: A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.

公开(公告)号：US20190147949A1

公开(公告)日：2019-05-16

申请号：US16007538

申请日：2018-06-13

Applicant: SK hynix Inc.

Inventor： Seung-Gyu JEONG ,  Jung-Hyun KWON ,  Do-Sun HONG ,  Won-Gyu SHIN

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C8/00 ,  G11C8/10 ,  G11C8/20 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/72 ,  G11C2213/76

Abstract: A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.