公开(公告)号：US20210142855A1

公开(公告)日：2021-05-13

申请号：US16878371

申请日：2020-05-19

Applicant: SK hynix Inc

Inventor： Chung Un NA

IPC: G11C16/14 ,  G11C16/26 ,  G11C7/10 ,  G06F12/0882 ,  G06F11/30 ,  G06F9/4401

Abstract: A memory system includes: a memory device including a memory cell array and a page buffer circuit, the memory device performing a data program operation or a data erase operation, suspending the data program operation or the data erase operation in response to a suspend command, performing a data read operation of storing read data from the memory cell array in the page buffer circuit in response to a read command, and performing a data output operation of outputting the read data stored in the page buffer circuit; and a memory controller outputting a pre-resume command to the memory device between a first time at which the data read operation is complete and a second time at which the data output operation starts.

公开(公告)号：US20210125679A1

公开(公告)日：2021-04-29

申请号：US16876407

申请日：2020-05-18

Applicant: SK hynix Inc.

Inventor： Min Hwan MOON ,  Chung Un NA

IPC: G11C29/38 ,  G06F12/0804

Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.

公开(公告)号：US20190196959A1

公开(公告)日：2019-06-27

申请号：US16055680

申请日：2018-08-06

Applicant: SK hynix Inc.

Inventor： Seung Gu JI ,  Chung Un NA ,  Byeong Gyu PARK

IPC: G06F12/02 ,  G06F12/0802 ,  G06F3/06

Abstract: A memory system includes a plurality of memory devices, each including a plurality of memory blocks; and a controller configured to evaluate performance grades of the plurality of memory blocks, form super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades, and write-access an opened super block, among the super blocks.