公开(公告)号：US20150123714A1

公开(公告)日：2015-05-07

申请号：US14074241

申请日：2013-11-07

Applicant: SILICON LABORATORIES INC.

Inventor： Ruifeng Sun ,  Mustafa H. Koroglu ,  Ramin Khoini Poorfard ,  Yu Su ,  Krishna Pentakota ,  Pio Balmelli

IPC: H03K17/16

CPC classification number: H03K17/16 ,  H03K2217/0063

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract translation: 与缓冲电路有关的技术。 在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。 在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。 在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。 在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。 在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。