Neural network system for performing learning, learning method thereof, and transfer learning method of neural network processor

    公开(公告)号:US11494646B2

    公开(公告)日:2022-11-08

    申请号:US16701841

    申请日:2019-12-03

    Abstract: A neural network system includes a processor and a memory. The processor is configured to perform learning including multiple learning iterations on multiple layers, to determine at least one layer in which the learning is interrupted among the multiple layers. The determination of the at least one layer in which the learning is interrupted is based on a result of comparing for each of the multiple layers a distribution of first weight values resulting from a first learning iteration with a distribution of second weight values resulting from a second learning iteration. The processor is also configured to perform a third learning iteration in layers except the at least one layer for which interruption of the learning has been determined. The memory stores first distribution information of the first weight values and second distribution information of the second weight values and is configured to provide the first distribution information and the second distribution information to the processor when the second learning iteration is completed.

    Streaming accelerators and streaming systems including the same

    公开(公告)号:US12190229B2

    公开(公告)日:2025-01-07

    申请号:US17341650

    申请日:2021-06-08

    Abstract: A streaming accelerator includes a first pool, a first switch bus, a second pool and a second switch bus. The first pool includes neural processing unit (NPU) bundles, and each of NPU bundles includes a plurality of NPUs. The first switch bus provides a first streaming data to a first selected NPU bundle and a second selected NPU bundle respectively. The second pool includes network interface card (NIC) bundles, and each of the NIC bundles includes an encoder and a NIC. The second switch bus provides a first intermediate streaming data and a second intermediate streaming data to a first selected NIC bundle and a second selected NIC bundle. The first selected NIC bundle encodes the first intermediate streaming data to generate a first encoded streaming data. The second selected NIC bundle encodes the second intermediate streaming data to generate a second encoded streaming data.

    Semiconductor memory device and electronic system the same

    公开(公告)号:US11567690B2

    公开(公告)日:2023-01-31

    申请号:US16790189

    申请日:2020-02-13

    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory core including a plurality of memory cells configured to store a plurality of data received from an external processor; and a statistical feature extractor disposed on a data path between the external processor and the memory core, the statistical feature extractor being configured to analyze statistical characteristics of the plurality of data, identify at least one statistical feature value associated with the statistical characteristics, store the at least one statistical feature value and transmit the at least one statistical feature value to the external processor.

    ELECTRONIC DEVICE FOR CONTROLLING DRIVING VEHICLE AND OPERATION METHOD OF THE ELECTRONIC DEVICE

    公开(公告)号:US20210326611A1

    公开(公告)日:2021-10-21

    申请号:US17146125

    申请日:2021-01-11

    Abstract: An electronic device configured to control a host vehicle includes: an image sensor configured to photograph a surrounding environment of the host vehicle; and a processor configured to perform an image processing operation based on a first image captured by the image sensor, and control the host vehicle based on the processing result, wherein the processor determines whether to use a high speed performance of the image processing operation based on a speed of the host vehicle, and the electronic device is configured such that when the high speed performance is not used, the processor performs the image processing operation by using a first image processing module, and when the high speed performance is used, the processor performs the image processing operation by using a second image processing module having less data throughput than the first image processing module.

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