公开(公告)号：US20190325979A1

公开(公告)日：2019-10-24

申请号：US16458933

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUN-JI KIM ,  JUNG-JUNE PARK ,  JEONG-DON IHM ,  BYUNG-HOON JEONG ,  YOUNG-DON CHOI

IPC: G11C29/02 ,  G11C5/06 ,  G11C7/10 ,  G11C16/06 ,  G11C16/26 ,  G11C16/10

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US20170047925A1

公开(公告)日：2017-02-16

申请号：US15141050

申请日：2016-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SIDDHARTH KATARE ,  JEONG-DON IHM

IPC: H03K17/687 ,  H03K19/0185

CPC classification number: H03K19/018521

Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.

Abstract translation: 缓冲电路包括第一和第二电流发生器，比较器，差分驱动器和反相器。 第一电流发生器输出对应于参考电压的第一电流。 第二电流发生器产生对应于输入极限电压的极限电流，并且输出具有等于极限电流大约一半的大小的第二电流。 第一电流和极限电流的大小由反馈电压控制。 比较器通过比较第一和第二电流产生反馈电压。 差分驱动器产生内部电流，并根据反馈电压控制内部电流。 内部电流的上限值和下限值的大小相对于基准值基本上彼此相等。 逆变器通过根据电源电压反转内部电流来产生输出电流。