公开(公告)号：US11581253B2

公开(公告)日：2023-02-14

申请号：US17503723

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghee Seo ,  Heonbok Lee ,  Tae-Yeol Kim ,  Daeyong Kim ,  Dohyun Lee

IPC: H01L23/498 ,  H01L29/78

Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

公开(公告)号：US10707126B2

公开(公告)日：2020-07-07

申请号：US16751744

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.