公开(公告)号：US10656442B2

公开(公告)日：2020-05-19

申请号：US15976912

申请日：2018-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba ,  Shinichi Kuwabara

IPC: G02F1/01 ,  G02F1/025

Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.

公开(公告)号：US10459162B2

公开(公告)日：2019-10-29

申请号：US16036455

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/122 ,  G02B6/125 ,  G02B6/12

Abstract: To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.

公开(公告)号：US10418321B2

公开(公告)日：2019-09-17

申请号：US15954213

申请日：2018-04-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Tetsuya Iida ,  Yasutaka Nakashiba

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L23/64 ,  H01L23/552 ,  H01L21/8238 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/495 ,  H01L23/532 ,  H01L21/265

Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

公开(公告)号：US09899446B2

公开(公告)日：2018-02-20

申请号：US15372775

申请日：2016-12-08

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14614

Abstract: A solid-state image sensing device capable of suppressing a dark current and transfer failure during a global shutter operation is provided. The solid-state image sensing device according to one embodiment includes: a semiconductor substrate having a main surface and a back surface being on the opposite side of the main surface; a well region arranged in contact with the main surface in the semiconductor substrate; a photoelectric conversion region arranged in contact with the main surface in the well region; a charge holding region arranged in contact with the main surface in the well region; a floating diffusion region arranged in contact with the main surface in the well region; a first transfer gate so formed as to face the well region and the charge holding region; and a second transfer gate so formed as to face the well region.

公开(公告)号：US09355890B2

公开(公告)日：2016-05-31

申请号：US13748873

申请日：2013-01-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida

IPC: H01L21/8242 ,  H01L21/762 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7824 ,  H01L21/30625 ,  H01L21/743 ,  H01L21/76243 ,  H01L21/76248 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a miniaturized semiconductor device having an SOI layer, in which: a silicon layer is formed over a semiconductor substrate via an BOX film; after the silicon layer is patterned by using a nitride film as a mask, an insulating film covering the surface of each of the nitride film, the silicon layer, and the BOX film is formed; subsequently, an opening, which penetrates the insulating film and the BOX film and which exposes the upper surface of the semiconductor substrate, is formed, and an epitaxial layer is formed in the opening; subsequently, the SOI region and a bulk silicon layer are formed over the semiconductor substrate by flattening the upper surface of the epitaxial layer with the use of the nitride film as an etching stopper film.

Abstract translation: 公开了一种具有SOI层的小型半导体器件，其中：通过BOX膜在半导体衬底上形成硅层; 在通过使用氮化物膜作为掩模对硅层进行图案化之后，形成覆盖氮化物膜，硅层和BOX膜中的每一个的表面的绝缘膜; 随后，形成穿透绝缘膜和BOX膜并露出半导体衬底的上表面的开口，并且在开口中形成外延层; 随后，通过使用氮化物膜作为蚀刻停止膜来平坦化外延层的上表面，在半导体衬底上形成SOI区域和体硅层。

公开(公告)号：US08779855B2

公开(公告)日：2014-07-15

申请号：US13904788

申请日：2013-05-29

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Akihiko Furukawa ,  Satoshi Yamakawa ,  Tsuyoshi Kawakami ,  Masao Kondo ,  Yutaka Hoshino

IPC: H03F3/26

CPC classification number: H03F3/211 ,  H03F1/56 ,  H03F3/26 ,  H03F2200/537 ,  H03F2203/21139

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract translation: 为了实现功率放大电路的频率特性的更宽的带宽，通过二次电感器将分别以不同频率匹配的差分推挽放大器的输出组合在一起，并输出组合信号。

公开(公告)号：US11630270B2

公开(公告)日：2023-04-18

申请号：US16811959

申请日：2020-03-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/42

Abstract: A semiconductor device includes a cladding layer and a first optical waveguide. The first optical waveguide is formed on the first cladding layer. An end surface of the first optical waveguide is inclined relative to a vertical line perpendicular to an upper surface of the cladding layer.

公开(公告)号：US11262500B2

公开(公告)日：2022-03-01

申请号：US16700580

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba ,  Seigo Namioka ,  Tomoo Nakayama

IPC: G02B6/122 ,  G02B6/13 ,  G02F1/025 ,  G02B6/12

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.

公开(公告)号：US11171086B2

公开(公告)日：2021-11-09

申请号：US16700485

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji Kubo ,  Koichi Ando ,  Eiji Io ,  Hideyuki Tajima ,  Tetsuya Iida

IPC: H01L23/522 ,  H01L23/373 ,  H01L21/768 ,  H01L27/06

Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

公开(公告)号：US11137560B2

公开(公告)日：2021-10-05

申请号：US16408100

申请日：2019-05-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/42 ,  H01L23/00 ,  H04B10/80 ,  H01L25/16

Abstract: The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements. A top surface of the first semiconductor chip is laminated with a top surface of the second semiconductor chip such that the first and second wirings are directly contacted with each other.