公开(公告)号：US20240363605A1

公开(公告)日：2024-10-31

申请号：US18454388

申请日：2023-08-23

Applicant: QUALCOMM Incorporated

Inventor： Darko POPOVIC ,  Miguel MIRANDA CORBALAN ,  Durodami LISK ,  Yue LI ,  Irfan KHAN

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/16 ,  H01L24/17 ,  H01L23/3107 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: A stacked integrated circuit (IC) device includes a first die including active circuitry and a power distribution network (PDN). The first die has a first set of contacts on a first side of the first die. The stacked IC device also includes a second die coupled, on a first side of the second die, to the first side of the first die. The second die also includes, on a second side of the second die, a second set of contacts to electrically connect circuitry of the second die to a substrate. The stacked IC device also includes an integrated capacitor device (ICD) coupled to the first side of the first die. The ICD is electrically connected, via the first set of contacts, to the PDN and includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

公开(公告)号：US20190043817A1

公开(公告)日：2019-02-07

申请号：US16132315

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Manoj KADADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising a WLP contact and a component within the WLP layer associated with a component depth. A conductive pillar is disposed on the WLP contact and comprises an opposite surface that forms an array pad. The package further comprises a mold over the WLP layer and at least partially surrounding the conductive pillar, wherein the mold compound and the array pad form a substantially planar land grid array (LGA) contact surface that is configured to couple the package to a land grid array. The LGA contact surface has a height that is equal to a selected LGA component height, and the selected LGA component height is equal to a difference between a keepout distance associated with a characteristic of the component within the WLP layer and the component depth.

公开(公告)号：US20250062285A1

公开(公告)日：2025-02-20

申请号：US18451971

申请日：2023-08-18

Applicant: QUALCOMM Incorporated

Inventor： Yue LI ,  Ryan LANE ,  Yangyang SUN ,  Charles David PAYNTER ,  Durodami LISK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16

Abstract: A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.