公开(公告)号：US20250098267A1

公开(公告)日：2025-03-20

申请号：US18469473

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Yan SUN ,  Deepak SHARMA ,  Shreesh NARASIMHA

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate stack including a first gate structure and a second gate structure offset in a first direction. The semiconductor structure includes a first source/drain (S/D) structure adjacent the first gate structure, a second S/D structure adjacent the second gate structure, a first backside conductive structure in contact with the first S/D structure, and a second backside conductive structure in contact with the second S/D structure. The semiconductor structure includes a third backside conductive structure disposed in a back portion of the semiconductor structure opposing a front portion of the semiconductor structure, extending along a second direction, and in contact with the first backside conductive structure and the second backside conductive structure.

公开(公告)号：US20250096075A1

公开(公告)日：2025-03-20

申请号：US18469501

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Yandong GAO ,  Peijie FENG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

Abstract: In an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (S/D) structures, a frontside (FS) inter-layer dielectric (FS-ILD) layer above the gate and S/D structures, FS metal zero (FM0) interconnects above the FS-ILD layer, a backside (BS) inter-layer dielectric (BS-ILD) layer below the gate and S/D structures, BS metal zero (BM0) interconnects below the BS-ILD layer, at least one FS source drain contact (FSDC) electrically connecting an FM0 interconnect to a top surface of an S/D structure, and at least one BS S/D contact (BSDC) electrically connecting a BMO interconnect to a bottom surface of an S/D structure. The semiconductor memory cell comprises NFETs and PFETs to form a cross-coupled inverter pair. For each inverter in the pair, one of VDD and VSS are provided by an FSDC and the other of VDD and VSS is provided by a BSDC.

公开(公告)号：US20250098302A1

公开(公告)日：2025-03-20

申请号：US18469505

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Deepak SHARMA

IPC: H01L27/12

Abstract: Compact logic cells using full backside connectivity are disclosed. In an aspect, a semiconductor device comprises a plurality of integrated circuit cells comprising: gates separated by source/drain (S/D) structures and comprising at least one channel extending through a metal structure and connecting adjacent S/D structures to each other, at least one gate forming a gate-all-around field effect transistor; an FS contact electrically connecting to an S/D structure; an FS contact electrically connecting to a gate; a frontside (FS) inter-layer dielectric (ILD) on the gates and S/D structures; FS metal zero interconnects disposed on the FS-ILD, one being electrically connected to an FS contact; a BS contact electrically connecting to an S/D structure; a BS contact electrically connecting to a gate; a backside (BS) ILD disposed on the gates and S/D structures; and BS metal zero interconnects disposed on the BS-ILD, one being electrically connected to a BS contact.

公开(公告)号：US20250096130A1

公开(公告)日：2025-03-20

申请号：US18824706

申请日：2024-09-04

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Deepak SHARMA

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a gate structure, disposed between a first vertical source/drain (S/D) structure and a second vertical S/D structure, the gate structure comprising a channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first vertical S/D structure to the second vertical S/D structure in a first horizontal direction through a vertical metal gate structure that at least partially surrounds the plurality of vertically-stacked, horizontal channels. The FET also comprises a backside inter-layer dielectric (ILD) layer disposed below the vertical metal gate structure, wherein a first thickness of the vertical metal gate structure below a bottom channel of the plurality of vertically-stacked, horizontal channels is larger than a second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically-stacked, horizontal channels.

公开(公告)号：US20240421209A1

公开(公告)日：2024-12-19

申请号：US18334226

申请日：2023-06-13

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Peijie FENG

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Disclosed are semiconductor devices and fabrication methods. A semiconductor device includes a first gate structure including a first set of channels disposed along a first direction through a first gate metal, and a first set of gate dielectrics disposed between the first set of channels and the first gate metal. The first set of gate dielectrics each have a first thickness. The semiconductor device further includes a second gate structure including a second set of channels disposed along the first direction through a second gate metal, and a second set of gate dielectrics disposed between the second set of channels and the second gate metal. The second set of gate dielectrics each have a second thickness. The second thickness is greater than the first thickness and the second set of channels is less in number than the first set of channels.