公开(公告)号：US12124401B2

公开(公告)日：2024-10-22

申请号：US18155499

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Francesco Gatta ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4295 ,  G06F13/24

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

公开(公告)号：US11907154B2

公开(公告)日：2024-02-20

申请号：US17861886

申请日：2022-07-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Francesco Gatta ,  Muhlis Kenan Ozel ,  Richard Dominic Wietfeldt

IPC: G06F13/40 ,  H04L7/00 ,  H04L7/04

CPC classification number: G06F13/4068 ,  H04L7/0066 ,  H04L7/0087 ,  H04L7/042 ,  G06F2213/40

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

公开(公告)号：US11513994B2

公开(公告)日：2022-11-29

申请号：US17148953

申请日：2021-01-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/362 ,  G06F13/40

Abstract: Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

公开(公告)号：US11041904B2

公开(公告)日：2021-06-22

申请号：US16589968

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Tapan Jyoti Chakraborty ,  Umesh Srikantiah ,  Rachana Rout

IPC: G01R31/317 ,  G01R31/3177

Abstract: In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.