公开(公告)号：US20200065260A1

公开(公告)日：2020-02-27

申请号：US16113141

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Pritha GHOSHAL ,  Niket CHOUDHARY ,  Ravi RAJAGOPALAN ,  Patrick EIBL ,  Brian STEMPEL ,  David Scott Ray ,  Thomas Philip SPEIER

IPC: G06F12/1027

Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

公开(公告)号：US20200004550A1

公开(公告)日：2020-01-02

申请号：US16024725

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Harsh THAKKER ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Kevin JAGET ,  James Norris DIEFFENDERFER ,  Michael MORROW ,  Pritha GHOSHAL ,  Yusuf Cagatay TEKMEN ,  Brian STEMPEL ,  Sang Hoon LEE ,  Manish GARG

IPC: G06F9/38 ,  G06F9/30

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

公开(公告)号：US20190034349A1

公开(公告)日：2019-01-31

申请号：US15658819

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： William MCAVOY ,  Brian STEMPEL ,  Spencer WILLIAMS ,  Robert Douglas CLANCY ,  Michael Scott MCILVAINE ,  Thomas Philip SPEIER

IPC: G06F12/1045 ,  G06F12/0891

Abstract: A translation lookaside buffer (TLB) index valid bit is set in a first line of a virtually indexed, virtually tagged (VIVT) cache. The first line of the VIVT cache is associated with a first TLB entry which stores a virtual address to physical address translation for the first cache line. The TLB index valid bit of the first line is cleared upon determining that the translation is no longer stored in the first TLB entry. An indication of a received invalidation instruction is stored. When a context synchronization instruction is received, the first line of the VIVT cache is cleared based on the TLB index valid bit being cleared and the stored indication of the invalidate instruction.

公开(公告)号：US20150074357A1

公开(公告)日：2015-03-12

申请号：US14195792

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Joseph G. MCDONALD ,  Jaya Prakash Subramaniam GANASAN ,  Thomas Philip SPEIER ,  Eric F. ROBINSON ,  Jason Lawrence PANAVICH ,  Thuong Q. TRUONG

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0824 ,  G06F12/0833 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A low latency cache intervention mechanism implements a snoop filter to dynamically select an intervener cache for a cache “hit” in a multiprocessor architecture of a computer system. The selection of the intervener is based on variables such as latency, topology, frequency, utilization, load, wear balance, and/or power state of the computer system.

Abstract translation: 低延迟高速缓存干预机制实现了窥探过滤器来动态地选择用于计算机系统的多处理器架构中的高速缓存“命中”的intervener缓存。 干扰器的选择基于诸如延迟，拓扑，频率，利用率，负载，磨损平衡和/或计算机系统的功率状态等变量。