公开(公告)号：US20240061795A1

公开(公告)日：2024-02-22

申请号：US17821399

申请日：2022-08-22

Applicant: QUALCOMM Incorporated

Inventor： Ravindranath DODDI ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA

IPC: G06F13/16

CPC classification number: G06F13/1694 ,  G06F2213/0026

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link state transition by a computing device. Embodiments may include comprising retrieving, by a PCIe controller, PCIe link configuration data from a memory for a PCIe link in a fast recovery low power state of a link training status and state machine (LTSSM), and re-initializing, by the PCIe controller, the PCIe link using the PCIe link configuration data retrieved from the memory. Embodiments may further include maintaining the PCIe link configuration data in the memory for the PCIe link in the fast recovery low power state of the LTSSM by providing auxiliary power to PCIe configuration registers for the PCIe controller.

公开(公告)号：US20250086136A1

公开(公告)日：2025-03-13

申请号：US18466299

申请日：2023-09-13

Applicant: QUALCOMM Incorporated

Inventor： Ravindranath DODDI ,  Umamaheshwaran V ,  Afreen HAIDER ,  Lekhya Pavani GODAVARTHI ,  Harinatha Reddy RAMIREDDY ,  James Lionel Panian ,  Ramacharan Sundararaman ,  Santhosh Reddy Akavaram

IPC: G06F13/42 ,  G06F15/78

Abstract: Various embodiments include methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets of a computing device. Embodiments may include transitioning a UCIe link in an active state having a first sideband that is active to the UCIe link in a reset state, and initializing at least one sideband for the UCIe link that is a different functional sideband of a multi-module chiplet than the first sideband following the reset state of the UCIe link. Embodiments may include reading sideband data configured to represent a functional sideband of the multi-module chiplet, and initializing the functional sideband as the at least one sideband. Embodiments may include reading sideband data configured to represent at least two functional sidebands of the multi-module chiplet, and initializing at least one functional sideband of the at least two functional sidebands as the at least one sideband.

公开(公告)号：US20240427710A1

公开(公告)日：2024-12-26

申请号：US18339904

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Ravindranath DODDI ,  Rajendra Varma PUSAPATI ,  Sonali JABREVA

IPC: G06F13/16

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.

公开(公告)号：US20240402751A1

公开(公告)日：2024-12-05

申请号：US18329462

申请日：2023-06-05

Applicant: QUALCOMM Incorporated

Inventor： Lekhya Pavani GODAVARTHI ,  Ravindranath DODDI ,  Harinatha Reddy RAMIREDDY ,  Afreen HAIDER ,  Umamaheshwaran V

IPC: G06F1/08

Abstract: Aspects relate to reduced training for main band chip module interconnection clock lines. In one example a method includes sending iterations of a first training pattern from a module of a first die to a module partner of a second die on a first main band clock line of a die-to-die connection, the die-to-die connection including a sideband, a main band comprising the first main band clock line, and at least one data line supported by at least the first main band clock line. An automatic result is received from the module partner through the sideband prior to completion of the iterations of the first training pattern, the automatic result indicating successfully receiving the training pattern. Data is communicated with the module partner through the main band using at least the first main band clock line in response to receiving the automatic result.

公开(公告)号：US20240111354A1

公开(公告)日：2024-04-04

申请号：US17959996

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Ravindranath DODDI ,  Ravi Kumar SEPURI

IPC: G06F1/3234 ,  G06F13/42

CPC classification number: G06F1/3278 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.