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11.发明公开公开(公告)号：US20240291284A1
公开(公告)日：2024-08-29
申请号：US18173518
申请日：2023-02-23
Applicant: QUALCOMM Incorporated
Inventor： Chunping SONG , Georgios Konstantinos PAPARRIZOS , Xinying DING , Jiwei CHEN , Guoyong Guo
CPC classification number: H02J7/0013 , H02J7/0047 , H02J7/007 , H02M3/158 , H02J2207/20 , H02M3/07
Abstract: Certain aspects of the present disclosure provide techniques and apparatus for supplying power, including battery charging. One example power supply circuit generally includes a switching regulator including an output node; a first battery node for coupling to a first battery; a second battery node for coupling to a second battery; a first switch coupled between the output node of the switching regulator and the first battery node; and a second switch coupled between the output node of the switching regulator and the second battery node. Such a power supply circuit may independently control and monitor the charging of multiple independent batteries without using multiple chargers, may balance the batteries during discharging, and may operate without a current limit switch.
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公开(公告)号：US20210036617A1
公开(公告)日：2021-02-04
申请号：US16944913
申请日：2020-07-31
Applicant: QUALCOMM Incorporated
Inventor： Chunping SONG , Hector Ivan Oporta , Sumukh Shevde
Abstract: Aspects of the present disclosure generally relate to multi-mode regulators. For example, the multi-mode regulator may include a first transistor having a first terminal coupled to an input voltage and a second terminal coupled to an output of the regulator, a second transistor having a first terminal coupled to the second terminal of the first transistor and a second terminal coupled to a reference potential, pulse width modulation (PWM) control logic having outputs coupled to gates of a first transistor and a second transistor, one or more error amplifiers, and a switch with a first terminal coupled to the gate of the first transistor and a second terminal coupled to the output of one of the one or more error amplifiers. By selectively configuring one or more components of the multi-mode regulator, the regulator may operate according to either a linear regulation mode or a switching regulation mode.
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公开(公告)号：US20190386481A1
公开(公告)日：2019-12-19
申请号：US16289836
申请日：2019-03-01
Applicant: QUALCOMM Incorporated
Inventor： Kunhee CHO , Hector Ivan OPORTA , Zhaohui ZHU , Chunping SONG
IPC: H02H7/12 , H02M1/32 , H02H1/00 , G01R19/165
Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for providing input current limiting and input over current protection for a power converter, such as a charge pump converter. One example method of power conversion generally includes sensing an average value associated with an input current for a power supply circuit, sensing an instantaneous value associated with the input current for the power supply circuit, limiting the input current when the sensed average value is greater than a first threshold, and activating over current protection for the power supply circuit when the sensed instantaneous value is greater than a second threshold.
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公开(公告)号：US20190379270A1
公开(公告)日：2019-12-12
申请号：US16004536
申请日：2018-06-11
Applicant: QUALCOMM Incorporated
Inventor： Stuart PULLEN , Michael BUI , Steve HAWLEY , Chunping SONG
Abstract: Methods and apparatus for current sensing and error correction in a switched-mode power supply composed of a high-side transistor coupled to a low-side transistor are described. One example method generally includes capturing a current associated with the low-side transistor at a first time corresponding to the low-side transistor turning off; capturing a current associated with the high-side transistor at a second time corresponding to a first delay after the high-side transistor turns on; capturing the current associated with the high-side transistor at a third time corresponding to the high-side transistor turning off; and applying a first correction current to a current-summing node of the current-sensing circuit for a first interval based on the first delay, wherein the first correction current is based on the captured current associated with the low-side transistor at the first time and on the captured current associated with the high-side transistor at the second time.
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公开(公告)号：US20250047122A1
公开(公告)日：2025-02-06
申请号：US18801144
申请日：2024-08-12
Applicant: QUALCOMM Incorporated
Inventor： Cheong KUN , Chunping SONG , Guoyong GUO
IPC: H02J7/00
Abstract: An apparatus is disclosed for parallel charging of at least one power storage unit. In example implementations, an apparatus includes a charging system. The charging system includes a first charger having a first current path and a second charger having a second current path. The charging system also includes a charging controller coupled to the first current path. The charging system further includes an indication path coupled between the second current path and the charging controller.
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Patent Agency Ranking
16.发明公开公开(公告)号：US20240322686A1
公开(公告)日：2024-09-26
申请号：US18189810
申请日：2023-03-24
Applicant: QUALCOMM Incorporated
Inventor： Sanghwa JUNG , Chunping SONG
IPC: H02M3/158 , H02M1/00 , H02M3/07 , H02M7/483 , H03K17/687
CPC classification number: H02M3/158 , H02M1/0032 , H02M3/07 , H02M7/4837 , H03K17/687
Abstract: Certain aspects of the present disclosure generally relate to a three-level buck converter operating in a two-level buck converter mode with a delay between deactivating transistors when transitioning between charge and discharge phases. For example, certain aspects provide a power supply circuit generally including: a first transistor and a second transistor coupled between an input node of the power supply circuit and a switching node of the power supply circuit; a third transistor and a fourth transistor coupled between a reference potential node of the power supply circuit and the switching node of the power supply circuit; and logic configured to control activation states of the first transistor, the second transistor, the third transistor, and the fourth transistor. In some aspects, the activation states of the first transistor and the second transistor are configured to be switched at different times between the charge phase and the discharge phase.
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公开(公告)号：US20230006555A1
公开(公告)日：2023-01-05
申请号：US17363948
申请日：2021-06-30
Applicant: QUALCOMM Incorporated
Inventor： Sanghwa JUNG , Chunping SONG , Ta-Tung YEN , Yue JING
Abstract: A three-level buck converter circuit configurable to transition between a three-level buck converter mode and a two-level buck converter mode and methods for regulating power using such a circuit. One example power supply circuit generally includes a three-level buck converter circuit and a control circuit coupled to the three-level buck converter circuit and configured to control operation of the three-level buck converter circuit between a three-level buck converter mode and a two-level buck converter mode. The three-level buck converter circuit generally includes a first switch, a second switch coupled to the first switch via a first node, a third switch coupled to the second switch via a second node, a fourth switch coupled to the third switch via a third node, a first capacitive element coupled between the first node and the third node, and an inductive element coupled between the second node and an output node.
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18.发明申请公开(公告)号：US20210083573A1
公开(公告)日：2021-03-18
申请号：US17021614
申请日：2020-09-15
Applicant: QUALCOMM Incorporated
Inventor： Ta-Tung YEN , Chunping SONG , Guoyong GUO , Hector Ivan OPORTA , Ahmed ABDELMOATY
Abstract: Techniques and apparatus for supplying power to gate drivers of a switched-mode power supply (SMPS) circuit. One example power supply circuit generally includes a SMPS circuit having a first input voltage node and a second input voltage node, and a charge pump. The charge pump generally includes a first capacitive element having a first terminal and a second terminal; a first switch coupled between a first input node of the charge pump and the first terminal of the first capacitive element; a second switch coupled between the second terminal of the first capacitive element and a second input node of the charge pump; a third switch coupled between the first terminal of the first capacitive element and the first input voltage node of the SMPS circuit; and a fourth switch coupled between the second terminal of the first capacitive element and the second input voltage node of the SMPS circuit.
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公开(公告)号：US20200161976A1
公开(公告)日：2020-05-21
申请号：US16683913
申请日：2019-11-14
Applicant: QUALCOMM Incorporated
Inventor： Chunping SONG , Jiwei CHEN , David King Wai LI
Abstract: Certain aspects of the present disclosure generally relate to an adaptive combination power supply circuit. The adaptive combination power supply circuit may be capable of switching between performing as a three-level buck converter and as a divide-by-two charge pump. One example power supply circuit generally includes a first transistor; a second transistor coupled to the first transistor via a first node; a third transistor coupled to the second transistor via a second node; a fourth transistor coupled to the third transistor via a third node; a capacitive element having a first terminal coupled to the first node and a second terminal coupled to the third node; an inductive element having a first terminal coupled to the second node; and a switch having a first terminal coupled to the first terminal of the inductive element, the switch having a second terminal coupled to a second terminal of the inductive element.
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公开(公告)号：US20180331624A1
公开(公告)日：2018-11-15
申请号：US15973787
申请日：2018-05-08
Applicant: QUALCOMM Incorporated
Inventor： Stuart PULLEN , Michael BUI , Chunping SONG , Jialei XU
CPC classification number: H02M3/158 , H02M1/088 , H02M3/156 , H02M3/1588 , H02M2001/0009
Abstract: Certain aspects of the present disclosure provide methods and apparatus for current sensing and error correction, or at least adjustment, for a switching regulator. One example current-sensing circuit generally includes a first amplifier, a buffer, a low-pass filter, a first switch coupled between an output of the first amplifier and an input of the buffer, a second switch coupled between the output of the first amplifier and an input of the low-pass filter, a third switch coupled between an output of the buffer and the input of the low-pass filter, and a fourth switch coupled between the input of the low-pass filter and a reference node for the circuit.
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