公开(公告)号：US10990117B2

公开(公告)日：2021-04-27

申请号：US16561839

申请日：2019-09-05

Applicant: QUALCOMM Incorporated

Inventor： Yue Chao ,  Marco Zanuso ,  Rajagopalan Rangarajan ,  Yiwu Tang

IPC: G05F1/575 ,  G05F1/595

Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

公开(公告)号：US10291242B1

公开(公告)日：2019-05-14

申请号：US15993254

申请日：2018-05-30

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Elbadry ,  Marco Zanuso ,  Tsai-Pi Hung ,  Francesco Gatta ,  Yunliang Zhu

IPC: H03L7/00 ,  H04B1/04 ,  H03L7/099 ,  H03L7/085 ,  H04L7/033

Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.

公开(公告)号：US10063366B2

公开(公告)日：2018-08-28

申请号：US15269320

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Marco Zanuso ,  Giovanni Marucci ,  Tsai-Pi Hung ,  Francesco Gatta ,  Bo Sun

IPC: H03D3/24 ,  H04L7/033 ,  H04W72/04 ,  H04B1/40 ,  H03L7/08 ,  H03L7/197 ,  H04B1/713

CPC classification number: H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.