公开(公告)号：US11558223B2

公开(公告)日：2023-01-17

申请号：US17648899

申请日：2022-01-25

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

公开(公告)号：US20180278405A1

公开(公告)日：2018-09-27

申请号：US15466469

申请日：2017-03-22

Applicant: Oracle International Corporation

Inventor： Yuhan Yao ,  Xun Zhang ,  Dawei Huang ,  Jianghui Su ,  Muthukumar Vairavan ,  Chaitanya Palusa

IPC: H04L7/00 ,  H04L7/02 ,  H04B1/16 ,  H03L7/08

CPC classification number: H04L7/0008 ,  H03L7/0807 ,  H04B1/16 ,  H04L7/02

Abstract: Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.

公开(公告)号：US11240073B2

公开(公告)日：2022-02-01

申请号：US16671146

申请日：2019-10-31

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.