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    Data processing system, data processing apparatus and handling method
    14.
    发明申请
    Data processing system, data processing apparatus and handling method 审中-公开
    数据处理系统，数据处理装置及处理方法

    公开(公告)号：US20070073911A1

    公开(公告)日：2007-03-29

    申请号：US11345939

    申请日：2006-02-02

    Applicant: Munetoshi Eguchi ,  Tomohiro Suzuki ,  Yuji Tamura ,  Tetsuya Ishikawa ,  Hiroyasu Nishimura ,  Tomoya Ogawa ,  Fumikage Uchida ,  Nao Moromizato ,  Masayuki Yasukaga

    Inventor： Munetoshi Eguchi ,  Tomohiro Suzuki ,  Yuji Tamura ,  Tetsuya Ishikawa ,  Hiroyasu Nishimura ,  Tomoya Ogawa ,  Fumikage Uchida ,  Nao Moromizato ,  Masayuki Yasukaga

    IPC: G06F3/00

    CPC classification number: G06F11/0751 ,  G06F11/0733

    Abstract: To provide a system capable of avoiding an apparatus anomaly such as a system hang, even when an anomaly condition of connection in the cable connecting the apparatuses occurs. A first apparatus 10 in the transmission side includes: a data processing device 12; a buffer register 22 in which the processing device writes the data to be sent; a transmission section 23 for sending the data stored in the buffer register to a second apparatus 40 connected by a cable 3; and a loop detection section 27 for detecting an anomaly condition of connection in the cable during the data transmission. When detecting the anomaly condition of connection in the loop detection section, the first apparatus clears the buffer register to release the processing device from the data writing waiting, and at the same time the first apparatus notifies the processing device of the occurrence of the anomaly condition.

    Abstract translation: 即使当连接设备的电缆中的连接的异常状况发生时，也能够提供能够避免诸如系统挂起的装置异常的系统。 发送侧的第一装置10包括：数据处理装置12; 缓冲寄存器22，处理装置写入要发送的数据; 发送部分23，用于将存储在缓冲寄存器中的数据发送到由电缆3连接的第二装置40; 以及用于在数据传输期间检测电缆中的连接的异常情况的环路检测部分27。 当检测到环路检测部分中的异常状况时，第一装置清除缓冲寄存器，以便从数据写入等待中释放处理装置，同时第一装置向处理装置通知异常条件的发生 。

    Image processing apparatus and image processing method
    15.
    发明申请
    Image processing apparatus and image processing method 审中-公开
    图像处理装置和图像处理方法

    公开(公告)号：US20060126095A1

    公开(公告)日：2006-06-15

    申请号：US11131157

    申请日：2005-05-16

    Applicant: Yuji Tamura ,  Tomohiro Suzuki ,  Tetsuya Ishikawa ,  Hiroyasu Nishimura ,  Tomoya Ogawa ,  Fumikage Uchida ,  Nao Moromizato ,  Masayuki Yasukaga

    Inventor： Yuji Tamura ,  Tomohiro Suzuki ,  Tetsuya Ishikawa ,  Hiroyasu Nishimura ,  Tomoya Ogawa ,  Fumikage Uchida ,  Nao Moromizato ,  Masayuki Yasukaga

    IPC: G06K15/00

    CPC classification number: H04N1/32144 ,  H04N1/00838

    Abstract: There is described an image processing apparatus which can add an additional image, such as a water mark, to an image to be processed and output those images. The image processing apparatus includes: an image signals obtaining section which obtains image signals corresponding to an image; a judgment section which judges whether date and time information meets date and time for output when the image is outputted based on the image signals; and an output section which outputs the image without an image relating to date and time information when the judgment section judges the date and time information meets the date and time for output, and outputs the image with the image relating to date and time information based on the date and time information when the judgment section judges the date and time information does not meet the date and time for output.

    Abstract translation: 描述了一种图像处理装置，其可以将诸如水印的附加图像添加到要处理的图像并输出这些图像。 图像处理装置包括：图像信号获取部，其获得与图像对应的图像信号; 判断部，根据图像信号判断日期和时间信息是否满足输出图像的日期和时间; 以及输出部分，当判断部分判断日期和时间信息满足输出的日期和时间时，输出图像而没有与日期和时间信息相关的图像，并且输出与日期和时间信息有关的图像的图像，基于 判断部判定日期和时间信息不满足输出日期和时间的日期和时间信息。

    Memory control apparatus
    16.
    发明申请
    Memory control apparatus 审中-公开
    存储器控制装置

    公开(公告)号：US20050210163A1

    公开(公告)日：2005-09-22

    申请号：US10946524

    申请日：2004-09-21

    Applicant: Tomohiro Suzuki ,  Yuji Tamura ,  Tetsuya Ishikawa ,  Hiroyasu Nishimura ,  Tomoya Ogawa ,  Fumikage Uchida ,  Nao Moromizato ,  Masayuki Yasukaga

    Inventor： Tomohiro Suzuki ,  Yuji Tamura ,  Tetsuya Ishikawa ,  Hiroyasu Nishimura ,  Tomoya Ogawa ,  Fumikage Uchida ,  Nao Moromizato ,  Masayuki Yasukaga

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28 ,  G06F13/36

    CPC classification number: G06F13/1673

    Abstract: A memory control section 10 is arranged between a bus 3 and a memory 4, if there is access to a predetermined virtual address space from the bus side, a virtual memory space control section 13 gains the corresponding access to small-capacity FIFO memories 11 and 12 from a memory 4, the DMA controller 14 permits data transfer to be carried out between the FIFO memories 11 and 12 and memory 4, asynchronously with the access to the virtual address space from the bus 3 side, the leading addresses of the transfer destination and source inside the memory 4, and the size of the data to be transferred are presetting the DMA controller 14 from the CPU 2 and others on the side of the bus 3.

    Abstract translation: 存储器控制部分10布置在总线3和存储器4之间，如果从总线侧访问预定的虚拟地址空间，则虚拟存储器空间控制部分13获得对小容量FIFO存储器11和 如图12所示，DMA控制器14允许在FIFO存储器11和12与存储器4之间进行数据传输，与从总线3侧到虚拟地址空间的访问异步，传送目的地的前导地址 并且存储器4内部的源，并且要传送的数据的大小从总线3侧的CPU 2等预先设置DMA控制器14。

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