Abstract:
A current source for producing a current that is proportional to absolute temperature (i.e., "PTAT") is disclosed. The current source is based upon a circuit having a pair of current mirrors, one based upon MOS transistors and the other based upon bipolar transistors, where each of two legs in the current source include the series connection of one of the MOS transistors with one of the bipolar transistors. Further included in the disclosed circuit is a series connection of three MOS startup transistors, useful in starting up the current source in a non-critical manner. A startup current source, sourcing a non-critical startup current, turns on one of the MOS startup transistors that is connected in current mirror fashion with the MOS transistor current mirror, turning on both current mirrors. As the output current increases, the current through the MOS startup transistors also increases, until equilibrium is achieved. Early effects in the bipolar transistor current mirror are eliminated by maintaining the gate-to-source voltage of the MOS transistors equal, without requiring cascode transistors, and thus maintaining low voltage operating capability.
Abstract:
A two-stage class-AB operational amplifier, that can be implemented either with bipolar or MOS transistors, includes a differential input circuit adapted to receive a differential input signal to produce an amplified differential output signal for application to first and second nodes. The differential input stage has a common-mode control circuit that produces first and second common-mode control voltages on the first and second nodes. The common-mode control voltages are combined with the amplified differential output signal on the first and second nodes to produce a first stage differential output signal. A high-swing output stage is connected to receive the first stage differential output signal. First and second current mirrors each have a mirror transistor to mirror an output current produced in response to the differential input signals on respective lines including the first and second nodes. The common-mode control circuit is in series with mirror transistors of the first and second current mirrors. A circuit clamps the first and second nodes at a voltage of 2V.sub.BE below the supply voltage, and clamps the voltage at the second node at a voltage of 2V.sub.BE above the reference potential, enabling the circuit to operate with improved power-supply rejection ratios.
Abstract:
A digital-to-analog converter has a bias block that provides first and second voltage outputs, and a bit cell having a switch for selectively connecting either a first or a second summing node to a current flow path depending upon the state of a binary input signal. An output bipolar transistor and a current source are connected in series between a supply voltage and a reference potential. A first MOS transistor is connected in the current flow path with its gate connected to the bipolar transistor. A base current compensating second MOS transistor is connected between the supply voltage and a base of the output bipolar transistor with its gate connected to the first voltage output of the amplifier. A resistor is connected between the base of the output bipolar transistor and the second voltage output of the amplifier. When a plurality of bit stages are provided, the resistor of each of the plurality of bit cells is sized according to a position of its associated cell in the bit order. The resistors may be sized as a power of 2 according to a position of its associated cell in the bit order, or, except for a most significant bit cell may be sized 2 times larger than the resistor of the most significant bit cell, with a plurality of equally sized resistors connecting adjacent bit cells in an R-2R network.
Abstract:
An operational amplifier input stage has at least two positive input transistors and one negative input transistor for providing more accurate and efficient limiting or rectification in limiter and rectifier circuits. The two positive input transistors are connected in parallel having a common drain connected to one side of a load and the negative input transistor's drain is connected to the other side of the load. The sources of all transistors are connected to a common node which is connected to a constant current source. This arrangement enables simplistic high accuracy limiting and rectifier circuits, having a reduced number of extrinsic components, thereby reducing unwanted speed limitations, to be realized. The operational amplifier input stage is also very useful in low supply circuit applications.
Abstract:
A differential input stage for an operational transconductance amplifier is provided with complementary input transistor pairs. For each pair, a diode dummy load is provided. When the common mode input signal is near the positive or negative supply voltage, one of the pairs turns off. The diode loads act to increase the current through the other pair when this occurs. This results in the provision of a constant transconductance over the entire common mode input range.
Abstract:
An operational amplifier having a differential signal input and an output has an input stage comprising a differential amplifier having a differential signal input and a differential signal output. The differential amplifier includes a first pair of transistors of opposite conductivity type having control elements connected to receive one side of the differential signal input, and second and third pairs of transistors of opposite conductivity type having control elements connected to receive another side of the differential signal input. The differential output of the differential amplifier is developed by outputs of the second and third pairs of transistors. A high-swing output section is connected to receive the differential signal output directly from the input stage. The differential amplifier has first and second current sources connected respectively between transistors of the first, second and third transistor pairs of a first conductivity type and a voltage supply, and between transistors of the first, second and third transistor pairs of a second conductivity type and a reference potential. A summing circuit is also provided in the input stage for summing the currents in the first, second, and third transistor pairs to produce the differential output of the input stage. The operational amplifier can be constructed of either bipolar or MOS transistors. One embodiment of the circuit provides an improved power supply rejection ratio through the use of current mirrors in a differential summing circuit to maintain output nodes of the input circuit at voltages within 2V.sub.BE of the supply voltage and reference potential, or ground.