公开(公告)号：US10242419B2

公开(公告)日：2019-03-26

申请号：US14843698

申请日：2015-09-02

Applicant: INTEL CORPORATION

Inventor： Rahul P. Sathe

IPC: G06T1/20 ,  G06T1/60

Abstract: In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.

公开(公告)号：US09916682B2

公开(公告)日：2018-03-13

申请号：US14925325

申请日：2015-10-28

Applicant: Intel Corporation

Inventor： Rahul P. Sathe ,  Bimal Poddar ,  Jon N. Hasselgren

IPC: G06T15/80 ,  G06K9/46 ,  G06T15/00 ,  G06T15/04

CPC classification number: G06T15/80 ,  G06K9/4604 ,  G06K9/4671 ,  G06K2009/4666 ,  G06T15/005 ,  G06T15/04 ,  G06T2200/04 ,  G06T2200/28 ,  G06T2210/36 ,  G06T2215/16

Abstract: The power consumption of processor-based devices may be reduced by reducing the consumption of power during graphics processing. In some embodiments, the precision of pixel shading in parts of images where artifacts are less objectionable may be reduced. For example, in areas the user is not directly looking at, precision may be reduced to save power. At the same time, because a person is not focusing on those regions, even if usually perceptible artifacts occur because of the reduced precision, an overall pleasing depiction may be achieved.

公开(公告)号：US20170132833A1

公开(公告)日：2017-05-11

申请号：US14937438

申请日：2015-11-10

Applicant: INTEL CORPORATION

Inventor： Rahul P. Sathe

IPC: G06T15/80 ,  G06T15/04 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04

Abstract: A graphics processing apparatus comprising a graphics processing pipeline including shader execution logic to execute shading instructions. The shading instructions causes the shader execution logic to programmatically determine a sample location for multiple pixels within a frame. The sample locations are determined based on a location of the pixel within the frame and can be determined by shader logic provided to the graphic processing apparatus by a graphics application.

公开(公告)号：US09449419B2

公开(公告)日：2016-09-20

申请号：US13628247

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Rahul P. Sathe ,  Tim Foley ,  Karthik Vaidyanathan

IPC: G06F12/02 ,  G06T15/00 ,  G06T1/60 ,  G06T17/20

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T17/20

Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.

Abstract translation: 根据一些实施例，当它们是冗余时，可以消除域着色器和/或细分器操作。 通过使用角落缓存，检查可以确定在域着色器和/或细分器中是否已经评估了一个给定的角点（无论是顶点还是四边形角），如果是，则可以重新使用先前操作的结果 执行可能增加功耗或降低速度的不必要的调用。

公开(公告)号：US09208602B2

公开(公告)日：2015-12-08

申请号：US14039732

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Rahul P. Sathe ,  Tim Foley

IPC: G09G5/36 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T2200/28

Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

Abstract translation: 设备可以包括索引缓冲器，用于存储索引流，该索引流具有对应于网格顶点和顶点高速缓存的多个索引条目，以存储网格的多个经处理的顶点。 该装置还可以包括处理器电路和顶点管理器，用于在处理器电路上执行以读取包括多个比特流条目的参考比特流，每个比特流条目对应于索引流的索引条目，并且移除经处理的顶点 当与所处理的顶点相对应的参考比特流条目的值等于定义的值时，从顶点高速缓存。