公开(公告)号：US20180217839A1

公开(公告)日：2018-08-02

申请号：US15423143

申请日：2017-02-02

申请人： INTEL CORPORATION

发明人： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3005

摘要： An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.

公开(公告)号：US20180004620A1

公开(公告)日：2018-01-04

申请号：US15705854

申请日：2017-09-15

申请人： Intel Corporation

发明人： Jonathan D. Combs ,  Michael W. Chynoweth ,  Jason W. Brandt ,  Corey D. Gough

IPC分类号： G06F11/34

CPC分类号： G06F11/348 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

摘要： Embodiments disclosed herein provide for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to track a non-precise event and to increment upon occurrence of the non-precise event, wherein the non-precise event comprises a first type of performance event that is not linked to an instruction in an instruction trace. The processing device also includes a first handler circuit to generate and store a first record, the first record comprising architectural metadata defining a state of the processing device at a time of generation of the first record, wherein the first handler circuit to generate records corresponding to precise events. The processing device further includes a second handler circuit communicably coupled to the first handler circuit, the second handler circuit to cause the first handler circuit to generate a second record for the non-precise event upon overflow of the performance counter.

公开(公告)号：US20180004512A1

公开(公告)日：2018-01-04

申请号：US15198856

申请日：2016-06-30

申请人： Intel Corporation

发明人： Jonathan D. Combs

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3016 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/3822 ,  G06F9/3855

摘要： A processor includes a core to execute decoded instructions and a front end. The front end includes two decode clusters and circuitry to receive data elements representing undecoded instructions, in program order, and to direct different subsets of the data elements to the two decode clusters. A splitter begins directing data elements to the first decode cluster, detects a cluster switching trigger condition, and directs a second subset of the data elements that immediately follows the first subset of data elements in program order to the second decode cluster. The trigger condition may be a predicated taken branch. The front end also includes circuitry to merge the decoded instructions generated by the first decode cluster and the decoded instructions generated by the second decode cluster to generate a sequence of decoded instructions in program order, based on a toggle indicator, and to provide it to the core for execution.

公开(公告)号：US09465680B1

公开(公告)日：2016-10-11

申请号：US14721819

申请日：2015-05-26

申请人： INTEL CORPORATION

发明人： Michael W. Chynoweth ,  Jonathan D. Combs ,  Angela D. Schmid ,  Kimberly C. Weier ,  Ahmad Yasin ,  Jason W. Brandt ,  Charlie J. Hewett ,  Seth Abraham ,  Matthew C. Merten

IPC分类号： G06F13/00 ,  G06F9/54 ,  G06F11/34 ,  G06F11/30

CPC分类号： G06F9/542 ,  G06F11/00 ,  G06F11/3024 ,  G06F11/3409

摘要： A processor and method are described for implementing performance monitoring using a fixed function performance counter. For example, one embodiment of an apparatus comprises: a fixed function performance counter to decrement or increment upon occurrence of an event in the processing device; a precise event based sampling (PEBS) enable control communicably coupled to the fixed function performance counter; a PEBS handler to generate and store a PEBS record comprising architectural metadata defining a state of the processing device at a time of generation of the PEBS record; and a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS enable control and the PEBS handler, the NPEBS module to cause the PEBS handler to generate the PEBS record for the event upon the fixed function performance counter reaching a specified value.

摘要翻译： 描述了使用固定功能性能计数器实现性能监视的处理器和方法。 例如，设备的一个实施例包括：固定功能性能计数器，用于在处理设备中发生事件时递减或递增; 精确的基于事件的采样（PEBS）使能控制可通信地耦合到固定功能性能计数器; PEBS处理器，用于生成和存储PEBS记录，其包括在生成PEBS记录时定义处理设备的状态的架构元数据; 以及可通信地耦合到PEBS使能控制和PEBS处理器的非精确事件采样（NPEBS）模块，NPEBS模块使固定功能性能计数器达到指定值时使PEBS处理程序生成事件的PEBS记录 。