公开(公告)号：US11853212B2

公开(公告)日：2023-12-26

申请号：US17713267

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Vesselina Papazova

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

公开(公告)号：US20230315638A1

公开(公告)日：2023-10-05

申请号：US17713264

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Winston Herring ,  Timothy Bronson ,  CHRISTIAN JACOBI

IPC: G06F12/084 ,  G06F12/0815 ,  G06F12/0897 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F9/34 ,  G06F9/3816 ,  G06F12/0897

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

公开(公告)号：US20230315636A1

公开(公告)日：2023-10-05

申请号：US17657169

申请日：2022-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jason D. Kohl ,  Winston Herring ,  Tu-An T. Nguyen ,  Gregory William Alexander ,  Timothy Bronson ,  CHRISTIAN JACOBI

IPC: G06F12/084

CPC classification number: G06F12/084

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

公开(公告)号：US10956637B2

公开(公告)日：2021-03-23

申请号：US16405467

申请日：2019-05-07

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F30/30 ,  G06F30/327 ,  G06F117/02

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

公开(公告)号：US20180203968A1

公开(公告)日：2018-07-19

申请号：US15408449

申请日：2017-01-18

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/70

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.