公开(公告)号：US20020197807A1

公开(公告)日：2002-12-26

申请号：US09885792

申请日：2001-06-20

Applicant: International Business Machines Corporation

Inventor： Basanth Jagannathan ,  Shwu-Jen Jeng ,  Jeffrey B. Johnson ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Kenneth J. Stein ,  Seshadri Subbanna

IPC: H01L021/331 ,  H01L021/8222

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract translation: 用于制造非自对准异质结双极晶体管的方法包括：在发射极堆叠中与多晶硅对准的PFET源极/漏极注入形成非本征基极区域，但不直接对准在该叠层中限定的发射极开口。 这通过使发射器基座宽于发射器开口来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

公开(公告)号：US20020139996A1

公开(公告)日：2002-10-03

申请号：US09822587

申请日：2001-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Basanth Jagannathan

IPC: H01L031/072

CPC classification number: H01L29/66242

Abstract: A method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions is disclosed. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxial layer defining the collector region. An oxide stack is formed upon the silicon epitaxial layer and a nitride layer is then formed upon the oxide stack. Next, an emitter opening is defined within the nitride layer before a base cavity is formed within the oxide stack. The base cavity extends laterally beyond the width of the emitter opening. A silicon-germanium epitaxial layer is grown within the base cavity, the silicon-germanium epitaxial layer defining the base region. Finally, a polysilicon layer is deposited upon said silicon-germanium epitaxial layer, the polysilicon layer defining the emitter region.

Abstract translation: 公开了一种用于制造具有集电极，基极和发射极区域的异质结双极晶体管的方法。 在本发明的示例性实施例中，该方法包括在衬底上形成硅外延层，硅外延层限定集电极区域。 在硅外延层上形成氧化层，然后在氧化层上形成氮化物层。 接下来，在氧化物堆内形成基腔之前，在氮化物层内限定发射极开口。 基座腔横向延伸超过发射器开口的宽度。 硅 - 锗外延层在基体腔内生长，硅 - 锗外延层限定基极区。 最后，在所述硅 - 锗外延层上沉积多晶硅层，所述多晶硅层限定发射极区域。

公开(公告)号：US20020132434A1

公开(公告)日：2002-09-19

申请号：US09811859

申请日：2001-03-19

Applicant: International Business Machines Corporation

Inventor： Gregory G. Freeman ,  Basanth Jagannathan ,  Shwu-jen Jeng ,  Jeffrey B. Johnson

IPC: H01L021/8222

CPC classification number: H01L29/66287 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/66242

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

Abstract translation: 本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。 本发明的优选实施例通过阶梯式收集器掺杂物分布提供改进的高速性能，其通过寄生电容的最小增加来减少发射极 - 集电极传播时间和寄生电阻。 优选的阶梯式收集器掺杂物分布包括浅植入物和更深的植入物。 浅的注入降低了基极 - 集电极空间电荷区域宽度，降低电阻，并调整集电极 - 基极击穿特性。 较深的植入物将埋藏的收集器连接到子集电极，并提供到子集电极的低电阻路径。 阶梯式收集器掺杂物分布对器件本征区域外部的集电极 - 基极电容的影响最小，因为较高掺杂剂由本征区域之外的外部碱性掺杂剂补偿或埋入其中。

公开(公告)号：US20020100917A1

公开(公告)日：2002-08-01

申请号：US09774126

申请日：2001-01-30

Applicant: International Business Machines Corporation

Inventor： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC: H01L031/0328 ,  H01L021/8249 ,  H01L031/0336

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract translation: 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。