公开(公告)号：US10832371B2

公开(公告)日：2020-11-10

申请号：US16236305

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Travis Schluessler ,  Gabor Liktor ,  Atsuo Kuwahara ,  Jefferson Amstutz

IPC: G06T15/10 ,  G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00 ,  G06T15/06

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US12026825B2

公开(公告)日：2024-07-02

申请号：US18306821

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Karthik Vaidyanathan

IPC: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06

CPC classification number: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06 ,  G06T2210/12

Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

公开(公告)号：US11670037B2

公开(公告)日：2023-06-06

申请号：US17735902

申请日：2022-05-03

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Karthik Vaidyanathan

IPC: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06

CPC classification number: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06 ,  G06T2210/12

Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

公开(公告)号：US10909741B2

公开(公告)日：2021-02-02

申请号：US16236176

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

IPC: G06T15/06 ,  G06T15/00 ,  G06T1/60

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.