公开(公告)号：US11137936B2

公开(公告)日：2021-10-05

申请号：US16930172

申请日：2020-07-15

Applicant: Google LLC

Inventor： Amin Farmahini ,  Benjamin Steel Gelb ,  Gurushankar Rajamani ,  Sukalpa Biswas

IPC: G06F3/00 ,  G06F3/06

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

公开(公告)号：US11748028B2

公开(公告)日：2023-09-05

申请号：US17993802

申请日：2022-11-23

Applicant: Google LLC

Inventor： Amin Farmahini ,  Benjamin Steel Gelb ,  Gurushankar Rajamani ,  Sukalpa Biswas

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0605 ,  G06F3/0679

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

公开(公告)号：US20230161498A1

公开(公告)日：2023-05-25

申请号：US17993802

申请日：2022-11-23

Applicant: Google LLC

Inventor： Amin Farmahini ,  Benjamin Steel Gelb ,  Gurushankar Rajamani ,  Sukalpa Biswas

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0605 ,  G06F3/0679

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

公开(公告)号：US11182159B2

公开(公告)日：2021-11-23

申请号：US17007569

申请日：2020-08-31

Applicant: Google LLC

Inventor： Thomas Norrie ,  Gurushankar Rajamani ,  Andrew Everett Phelps ,  Matthew Leever Hedlund ,  Norman Paul Jouppi

IPC: G06F9/30 ,  G06N3/04 ,  G06F13/28

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.

公开(公告)号：US20210311658A1

公开(公告)日：2021-10-07

申请号：US17348558

申请日：2021-06-15

Applicant: Google LLC

Inventor： Amin Farmahini ,  Benjamin Steel Gelb ,  Gurushankar Rajamani ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

公开(公告)号：US20250045238A1

公开(公告)日：2025-02-06

申请号：US18792169

申请日：2024-08-01

Applicant: Google LLC

Inventor： Horia Alexandru Toma ,  Gurushankar Rajamani ,  Sukalpa Biswas ,  Robert S. Sprinkle

IPC: G06F13/42

Abstract: The present application relates to systems and methods for providing high bandwidth connections between memory and computing units. For example, memory units can be configured to perform concurrent read and write operations in parallel to one another. The memory units can also be configured to alter the relative bandwidths that are available for the read and write operations. For example, bi-directional transmission interfaces of a memory unit can be assigned to operate as uni-directional interfaces that are a part of either a data input path or a data output path.

公开(公告)号：US20250028661A1

公开(公告)日：2025-01-23

申请号：US18223332

申请日：2023-07-18

Applicant: Google LLC

Inventor： Horia Alexandru Toma ,  Zuowei Shen ,  William F. Edwards, JR. ,  Gurushankar Rajamani ,  Hong Liu ,  Ilyas Mohammed

IPC: G06F13/16

Abstract: The disclosure provides for high bandwidth processing through the sharing of memory dies over a plurality of computing dies via an optical interchange. The optical interchange may be configured so as to operate as both an optical switch and optical demultiplexer. The optical switch configuration for the optical interchange allows for data to be written from any computing die to one of a plurality of memory dies via an optical connection. The optical demultiplexer configuration allows for data to be broadcast from a memory die to a plurality of the computing dies.

公开(公告)号：US20240394141A1

公开(公告)日：2024-11-28

申请号：US18324431

申请日：2023-05-26

Applicant: Google LLC

Inventor： Gurushankar Rajamani ,  Horia Alexandru Toma ,  Le Wang ,  Spoorthy Nanjaiah ,  Albert Forte Magyar ,  Xiaoming Wang

IPC: G06F11/10 ,  G06F12/02

Abstract: The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.

公开(公告)号：US11934826B2

公开(公告)日：2024-03-19

申请号：US17530869

申请日：2021-11-19

Applicant: Google LLC

Inventor： Thomas Norrie ,  Gurushankar Rajamani ,  Andrew Everett Phelps ,  Matthew Leever Hedlund ,  Norman Paul Jouppi

IPC: G06F9/30 ,  G06F13/28 ,  G06F15/78 ,  G06N3/045

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3004 ,  G06F13/28 ,  G06F15/7821 ,  G06N3/045

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.

公开(公告)号：US20220374692A1

公开(公告)日：2022-11-24

申请号：US17713122

申请日：2022-04-04

Applicant: Google LLC

Inventor： Gurushankar Rajamani ,  Alice Kuo

IPC: G06N3/063 ,  G06F3/06 ,  G06N3/04

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for interleaving memory requests to accelerate memory accesses at a hardware circuit configured to implement a neural network model. A system generates multiple requests that are processed against a memory of the system. Each request is used to retrieve data from the memory. For each request, the system generates multiple sub-requests based on a respective size of the data to be retrieved using the request. The system generates a sequence of interleaved sub-requests that includes respective sub-requests of a first request interleaved among respective sub-requests of a second request. Based on the sequence of interleaved sub-requests, a module of the system receives respective portions of data accessed from different address locations of the memory. The system processes each of the respective portions of data to generate a neural network inference using the neural network model implemented at the hardware circuit.