公开(公告)号：US20240394141A1

公开(公告)日：2024-11-28

申请号：US18324431

申请日：2023-05-26

Applicant: Google LLC

Inventor： Gurushankar Rajamani ,  Horia Alexandru Toma ,  Le Wang ,  Spoorthy Nanjaiah ,  Albert Forte Magyar ,  Xiaoming Wang

IPC: G06F11/10 ,  G06F12/02

Abstract: The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.

公开(公告)号：US12242338B2

公开(公告)日：2025-03-04

申请号：US18324431

申请日：2023-05-26

Applicant: Google LLC

Inventor： Gurushankar Rajamani ,  Horia Alexandru Toma ,  Le Wang ,  Spoorthy Nanjaiah ,  Albert Forte Magyar ,  Xiaoming Wang

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02

Abstract: The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.

公开(公告)号：US20250103426A1

公开(公告)日：2025-03-27

申请号：US18969998

申请日：2024-12-05

Applicant: Google LLC

Inventor： Gurushankar Rajamani ,  Horia Alexandru Toma ,  Le Wang ,  Spoorthy Nanjaiah ,  Albert Forte Magyar ,  Xiaoming Wang

IPC: G06F11/10 ,  G06F12/02

Abstract: The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.