公开(公告)号：US06258656B1

公开(公告)日：2001-07-10

申请号：US09395316

申请日：1999-09-13

Applicant: Gerrit Lange ,  Till Schlösser

Inventor： Gerrit Lange ,  Till Schlösser

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/88

Abstract: A capacitor on a semiconductor configuration is formed with a high-&egr; dielectric or a ferroelectric material. A first noble-metal-containing storage electrode has a plurality of horizontal lamellae connected to one another via a support structure. The support structure is arranged on one or preferably two opposite external flanks of the lamellae. During production, firstly (inter alia by deposition of a sequence of layers with an alternating low and high etching rate) a fin stack negative mold, in particular made from p+-polysilicon, is formed, which is then filled conformally with the electrode material.

Abstract translation: 半导体结构的电容器由高电介质或铁电材料形成。 第一含贵金属的储存电极具有经由支撑结构彼此连接的多个水平薄片。 支撑结构布置在薄片的一个或优选两个相对的外侧面上。 在生产过程中，首先（尤其是通过沉积具有交替的低和高蚀刻速率的一系列层），形成特别由p +多晶硅制成的翅片堆叠阴模，然后将其与电极材料共形地填充。

公开(公告)号：US6117790A

公开(公告)日：2000-09-12

申请号：US302655

申请日：1999-04-30

Applicant: Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

Inventor： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82

Abstract: A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

Abstract translation: 一种制造用于半导体存储器配置的电容器的方法。 在这种情况下，将可选择的可蚀刻材料施加到导电支撑件，该导电支撑件通过绝缘体层中的接触孔连接到半导体本体并且被图案化。 在其上施加第一导电层并图案化。 在第一导电层中引入一个孔，通过该孔蚀刻可选择性蚀刻的材料。 在该过程中在第一导电层下方产生空腔。 空腔的内表面和第一导电层的外表面设置有电介质层，第二导电层被施加并图案化。