公开(公告)号：US09588240B1

公开(公告)日：2017-03-07

申请号：US14923812

申请日：2015-10-27

Applicant: General Electric Company

Inventor： Ibrahim Issoufou Kouada ,  Brian David Yanoff ,  Jonathan David Short ,  Jianjun Guo ,  Biju Jacob

IPC: G01T1/24

CPC classification number: G01T1/247 ,  H01L27/14641 ,  H04N5/32 ,  H04N5/3415 ,  H04N5/37455 ,  H04N5/37457

Abstract: An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines—selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.

Abstract translation: 一个成像器瓦片，包括具有片上数字化电子读出电路的四面可折叠亚像素像素阵列。 从多个成像器中形成的像素组。 包括用于每个像素分组的缓冲放大器的读出电子器件连接到可压缩成像器的相应输出。 共享模拟前端连接到像素分组的相应缓冲放大器。 相对于共享模拟前端在公共中心位置的模数转换器包括用于单独选择输出，时钟输入线和共享数字输出线的三条数据线选择输入/输出线。 来自相应缓冲放大器的像素输出可通过在选择输入/输出线上提供的数据进行寻址，并且在共享数字输出线上提供像素输出。 连接到可编程逻辑器件的I / O线，其中成像器串行数据输入被输出为大量并行的数据流。

公开(公告)号：US20160358957A1

公开(公告)日：2016-12-08

申请号：US15077006

申请日：2016-03-22

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Jianjun Guo ,  Sergei Ivanovich Dolinsky ,  Jonathan David Short

IPC: H01L27/146 ,  H01L31/0352

CPC classification number: H01L27/14612 ,  H01L27/14663 ,  H01L31/035272

Abstract: Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include an epitaxial layer, a high voltage region formed in the epitaxial layer, a low voltage region formed in the epitaxial layer, and an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.

Abstract translation: 本文提供了固态光电倍增管的实施例。 在一些实施例中，固体光电倍增器可以包括外延层，在外延层中形成的高电压区域，形成在外延层中的低电压区域和设置在高电压区域和低电压区域之间的中间区域，其中 所述高电压区域经由所述中间区域电耦合到所述低电压区域，并且其中所述外延层的至少一部分设置在所述高压区域和中间区域之间以及所述低电压区域和所述中间区域之间。

公开(公告)号：US20150035967A1

公开(公告)日：2015-02-05

申请号：US13958209

申请日：2013-08-02

Applicant: General Electric Company

Inventor： Robert Gideon Wodnicki ,  Sora Kim ,  Ansas Matthias Kasten ,  Kevin Coombs ,  Clark Alexander Bendall ,  Jonathan David Short

IPC: H04N7/18

CPC classification number: H04N7/183 ,  A61B1/045 ,  H04N5/23203 ,  H04N5/3765 ,  H04N2005/2255

Abstract: An embedded imaging system in one embodiment includes an encoding module, an imaging module, and a cable. The encoding module is disposed proximate to a proximal end of the system, and is configured to encode frame synchronizing information into timing information comprising a reference clock. The imaging module is disposed proximate the distal end, and includes an image capture device configured to obtain imaging information and a decoding module. The decoding control module is configured to obtain the timing information, to decode the timing information to obtain recovered frame synchronizing information, and to control the image capture device using the recovered frame synchronizing information. The cable is interposed between the proximal end and the distal end, and is configured for passage therethrough of the timing information and the imaging information.

Abstract translation: 一个实施例中的嵌入式成像系统包括编码模块，成像模块和电缆。 编码模块靠近系统的近端设置，并且被配置为将帧同步信息编码成包括参考时钟的定时信息。 成像模块设置在远端附近，并且包括被配置为获得成像信息和解码模块的图像捕获装置。 解码控制模块被配置为获得定时信息，以解码定时信息以获得恢复的帧同步信息，并且使用恢复的帧同步信息来控制图像捕获设备。 电缆插入在近端和远端之间，并且被构造成用于通过定时信息和成像信息。

公开(公告)号：US09337233B1

公开(公告)日：2016-05-10

申请号：US14570089

申请日：2014-12-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Sabarni Palit ,  James Wilson Rose ,  Peter Micah Sandvik ,  Jonathan David Short ,  Ching-Yeu Wei ,  Xingguang Zhu

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146

CPC classification number: H01L27/14663 ,  H01L27/14643 ,  H01L27/14661

Abstract: Embodiments of a photodiode array are provided herein. In some embodiments, a photodiode array may include a semiconductor layer configured to convert photons into analog electrical signals; and a passive layer having a first surface and a second surface disposed opposite the first surface, wherein the semiconductor layer is coupled to the first surface, and wherein the passive layer is configured to have a signal receiving component coupled directly to the second surface of the passive layer.

Abstract translation: 本文提供了光电二极管阵列的实施例。 在一些实施例中，光电二极管阵列可以包括配置成将光子转换成模拟电信号的半导体层; 以及无源层，其具有与所述第一表面相对设置的第一表面和第二表面，其中所述半导体层耦合到所述第一表面，并且其中所述无源层被配置为具有直接耦合到所述第一表面的所述第二表面的信号接收部件 被动层。

公开(公告)号：US20140301534A1

公开(公告)日：2014-10-09

申请号：US13857624

申请日：2013-04-05

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Naresh Kesavan Rao ,  James Wilson Rose ,  Christopher David Unger ,  Abdelaziz Ikhlef ,  Jonathan David Short

IPC: G01T1/20 ,  G01N23/04

CPC classification number: G01T1/247 ,  A61B6/42 ,  A61B6/4233 ,  H01L27/14661 ,  H01L27/14663

Abstract: Improved imaging systems are disclosed. More particularly, the present disclosure provides for an improved image sensor assembly for an imaging system, the image sensor assembly having an integrated photodetector array and its associated data acquisition electronics fabricated on the same substrate. By integrating the electronics on the same substrate as the photodetector array, this thereby reduces fabrications costs, and reduces interconnect complexity. Since both the photodiode contacts and the associated electronics are on the same substrate/plane, this thereby substantially eliminates certain expensive/time-consuming processing techniques. Moreover, the co-location of the electronics next to or proximal to the photodetector array provides for a much finer resolution detector assembly since the interconnect bottleneck between the electronics and the photodetector array is substantially eliminated/reduced. The co-location of the electronics next to or proximal to the photodetector array also enables/facilitates programmable pixel configuration for optimal image quality.

Abstract translation: 公开了改进的成像系统。 更具体地，本公开提供了一种用于成像系统的改进的图像传感器组件，该图像传感器组件具有集成的光电检测器阵列及其在相同基板上制造的相关联的数据采集电子装置。 通过将电子元件集成在与光电检测器阵列相同的基板上，由此降低了制造成本，并降低了互连复杂度。 由于光电二极管触点和相关联的电子器件都在相同的衬底/平面上，因此基本上消除了某些昂贵/耗时的处理技术。 此外，由于电子设备和光电检测器阵列之间的互连瓶颈基本上被消除/减少，所以电子器件靠近光电检测器阵列的共同定位提供了更精细的分辨率检测器组件。 靠近或接近光电检测器阵列的电子设备的共同位置也使得/促进可编程像素配置以获得最佳图像质量。

公开(公告)号：US20130230134A1

公开(公告)日：2013-09-05

申请号：US13853192

申请日：2013-03-29

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Wen Li ,  Jonathan David Short ,  George Edward Possin

IPC: H01L27/146

CPC classification number: H01L27/14601 ,  A61B6/032 ,  G01T1/2018 ,  G01T1/249 ,  H01L31/105

Abstract: An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.

Abstract translation: 减少光电二极管热增益系数的装置包括具有光照射侧的体半导体材料。 体半导体材料包括少数电荷载流子扩散长度特性，其被配置为基本上匹配预定的空穴扩散长度值和被配置为基本匹配预定的光电二极管层厚度的厚度。 该装置还包括耦合到体半导体材料的光照射侧的死层，该死层具有被配置为基本匹配预定厚度值的厚度，并且其中由少数载体产生的增益热系数的绝对值 体半导体材料的扩散长度特性被配置为基本上匹配由于死层的厚度而导致的增益热系数的绝对值。