公开(公告)号：US09588240B1

公开(公告)日：2017-03-07

申请号：US14923812

申请日：2015-10-27

Applicant: General Electric Company

Inventor： Ibrahim Issoufou Kouada ,  Brian David Yanoff ,  Jonathan David Short ,  Jianjun Guo ,  Biju Jacob

IPC: G01T1/24

CPC classification number: G01T1/247 ,  H01L27/14641 ,  H04N5/32 ,  H04N5/3415 ,  H04N5/37455 ,  H04N5/37457

Abstract: An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines—selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.

Abstract translation: 一个成像器瓦片，包括具有片上数字化电子读出电路的四面可折叠亚像素像素阵列。 从多个成像器中形成的像素组。 包括用于每个像素分组的缓冲放大器的读出电子器件连接到可压缩成像器的相应输出。 共享模拟前端连接到像素分组的相应缓冲放大器。 相对于共享模拟前端在公共中心位置的模数转换器包括用于单独选择输出，时钟输入线和共享数字输出线的三条数据线选择输入/输出线。 来自相应缓冲放大器的像素输出可通过在选择输入/输出线上提供的数据进行寻址，并且在共享数字输出线上提供像素输出。 连接到可编程逻辑器件的I / O线，其中成像器串行数据输入被输出为大量并行的数据流。