公开(公告)号：US20180131946A1

公开(公告)日：2018-05-10

申请号：US15806200

申请日：2017-11-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Mi Young LEE ,  Byung Jo KIM ,  Ju-Yeob KIM ,  Jin Kyu KIM ,  Seong Min KIM ,  Joo Hyun LEE

IPC: H04N19/169 ,  G06F17/30 ,  G06N3/08 ,  G06N3/063 ,  H04N19/13 ,  G06K9/62

CPC classification number: H04N19/169 ,  G06F16/50 ,  G06K9/6256 ,  G06K9/6267 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  H04N19/13 ,  H04N19/48

Abstract: Provided is a convolution neural network system including an image database configured to store first image data, a machine learning device configured to receive the first image data from the image database and generate synapse data of a convolution neural network including a plurality of layers for image identification based on the first image data, a synapse data compressor configured to compress the synapse data based on sparsity of the synapse data, and an image identification device configured to store the compressed synapse data and perform image identification on second image data without decompression of the compressed synapse data.

公开(公告)号：US20180129935A1

公开(公告)日：2018-05-10

申请号：US15806111

申请日：2017-11-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Kyu KIM ,  Byung Jo KIM ,  Seong Min KIM ,  Ju-Yeob KIM ,  Mi Young LEE ,  Joo Hyun LEE

IPC: G06N3/063 ,  G06N3/04 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/082

Abstract: Provided is a convolutional neural network system including a data selector configured to output an input value corresponding to a position of a sparse weight from among input values of input data on a basis of a sparse index indicating the position of a nonzero value in a sparse weight kernel, and a multiply-accumulate (MAC) computator configured to perform a convolution computation on the input value output from the data selector by using the sparse weight kernel.

公开(公告)号：US20170149589A1

公开(公告)日：2017-05-25

申请号：US15348771

申请日：2016-11-10

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Kyu KIM

IPC: H04L27/26

CPC classification number: H04L27/265 ,  G06F9/3001 ,  G06F17/141 ,  G06F17/142

Abstract: Provided is a fully parallel fast Fourier transformer of N-point, where N is a natural number, including a bit-reversal arranging block configured to rearrange an order of N input complex number samples, a plurality of first processors configured to perform, in a plurality of group units, a 16-point FFT on the rearranged complex number samples, a twiddle factor multiplier configured to multiply outputs of the plurality of first processors by twiddle factors, a first group rearranging block configured to rearrange outputs of the twiddle factor multiplier in the plurality of group units, a plurality of second processors configured to perform, in the plurality of group units, 16-point FFT on the complex number samples grouped by the first group rearranging block, and a second group rearranging block configured to rearrange outputs of the plurality of second processors to output under a same arrangement criterion as the first group rearranging block.