Microphone system
    11.
    发明授权

    公开(公告)号:US12143782B2

    公开(公告)日:2024-11-12

    申请号:US17974323

    申请日:2022-10-26

    Abstract: A microphone system is disclosed, comprising: a microphone array and a processing unit. The microphone array comprises Q microphones that detect sound and generate Q audio signals. The processing unit is configured to perform operations comprising: spatial filtering over the Q audio signals using a trained model based on at least one target beam area (TBA) and coordinates of the Q microphones to generate a beamformed output signal originated from ω target sound source inside the at least one TBA, where ω>=0. Each TBA is defined by r time delay ranges for r combinations of two microphones out of the Q microphones, where Q>=3 and r>=1. A dimension of a first number for locations of all sound sources able to be distinguished by the processing unit increases as a dimension of a second number for a geometry formed by the Q microphones increases.

    Apparatus and method for own voice suppression

    公开(公告)号:US11622208B2

    公开(公告)日:2023-04-04

    申请号:US17324717

    申请日:2021-05-19

    Abstract: An own voice suppression apparatus applicable to a hearing aid is disclosed. The own voice suppression apparatus comprises: an air conduction sensor, an own voice indication module and a suppression module. The air conduction sensor is configured to generate an audio signal. The own voice indication module is configured to generate an indication signal according to at least one of user's mouth vibration information and user's voice feature vector comparison result. The suppression module coupled to the air conduction sensor and the own voice indication module is configured to generate an own-voice-suppressed signal according to the indication signal and the audio signal.

    Processing apparatus and method for artificial neuron

    公开(公告)号:US11068775B2

    公开(公告)日:2021-07-20

    申请号:US15910404

    申请日:2018-03-02

    Abstract: A processing apparatus applied in an artificial neuron is disclosed. The processing apparatus comprises a parser, a lookup array, a summing circuit and a MAC circuit. The parser parses one of M packets to extract a non-zero weight value from a header of the one packet, to identify a plurality of bit positions with a specified digit from a payload of the one packet, and to output the non-zero weight value and the bit positions in parallel. The lookup array contains N synapse values and is indexed by the bit positions in parallel to generate a plurality of match values. The summing circuit sums up the match values to generate a sum value. The MAC circuit generates a product of the non-zero weight value and the sum value, and generates an accumulate value based on the product and at least one previous accumulate value.

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