-
公开(公告)号：US09997136B2
公开(公告)日：2018-06-12
申请号：US14787893
申请日：2015-04-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Kun Cao , Zhongyuan Wu , Chen Song
IPC: G09G5/10 , G09G3/3266 , G11C19/28
CPC classification number: G09G5/10 , G09G3/3258 , G09G3/3266 , G09G2300/0408 , G09G2310/0262 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/043 , G09G2320/045 , G09G2330/021 , G09G2330/10 , G09G2330/12 , G11C19/287
Abstract: A display circuit and a driving method thereof and a display apparatus are provided. The display circuit comprises a pixel unit (11), a first gate driving unit (12) and a second gate driving unit (13); wherein the first gate driving unit (12) is configured to input a first gate driving signal to the pixel unit (11); the second gate driving unit (13) is configured to input a second gate driving signal to the pixel unit (11); and the pixel unit (11) is configured to perform threshold compensating and gray scale displaying simultaneously under the control of the first gate driving signal and the second gate driving signal. The apparatus and method is capable of reducing the complexity in design of the display circuit, which is advantageous for raising density of pixels of the display panel. The apparatus and method are applicable to manufacture a display.
-
公开(公告)号：US11025266B2
公开(公告)日：2021-06-01
申请号：US16489150
申请日：2019-03-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Tangxiang Wang , Chen Song , Zhan Gao , Yi Chen
Abstract: Embodiments of the present disclosure provide a digital-to-analog converter, a conversion circuit and a display device. An M-bit digital-to-analog converter includes a higher M−N-bit digital-to-analog conversion circuit, a voltage conversion circuit, an output circuit. The higher M−N-bit digital-to-analog conversion circuit includes: a higher M−N-bit voltage division generation circuit, a first voltage selection circuit. The first voltage selection circuit selects a first voltage from the higher M−N-bit voltage division generation circuit based on a higher M−N-bit digital signal, to be output from a first voltage end. The voltage conversion circuit charges a capacitor circuit under the control of a first switch circuit and a second switch circuit, and discharges a second voltage to a second voltage end through the capacitor circuit. The output circuit controls the first voltage and the second voltage based on a lower N-bit digital signal, generates an analog voltage signal corresponding to an M-bit digital signal.
-
公开(公告)号：US10236904B1
公开(公告)日：2019-03-19
申请号：US15987201
申请日：2018-05-23
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Tangxiang Wang , Chen Song
IPC: H03M1/76 , G09G3/3225
Abstract: Embodiments of the present application provide a digital-to-analog conversion circuit, a method thereof and a display apparatus. The digital-to-analog conversion circuit comprises a voltage dividing sub-circuit, having 2m of voltage dividing signal terminals and 2n-m−1 of sub-voltage dividing signal terminals; a first voltage selecting sub-circuit, configured to receive the first bit to the (n−m)th bit of the digital signal, and convert it into a first analog signal; a second voltage selecting sub-circuit, configured to receive the (n-m+1)th bit to the nth bit of the digital signal and to convert it into a second analog signal; and a buffering sub-circuit, configured to generate an analog signal based on the first analog signal, the second analog signal and the signal from the ith voltage dividing signal terminal and to output the analog signal to an analog signal outputting terminal of the digital-to-analog conversion circuit.
-
公开(公告)号：US09966041B2
公开(公告)日：2018-05-08
申请号：US14787893
申请日：2015-04-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Kun Cao , Zhongyuan Wu , Chen Song
IPC: G09G5/10 , G09G3/3266 , G11C19/28
Abstract: A display circuit and a driving method thereof and a display apparatus are provided. The display circuit comprises a pixel unit (11), a first gate driving unit (12) and a second gate driving unit (13); wherein the first gate driving unit (12) is configured to input a first gate driving signal to the pixel unit (11); the second gate driving unit (13) is configured to input a second gate driving signal to the pixel unit (11); and the pixel unit (11) is configured to perform threshold compensating and gray scale displaying simultaneously under the control of the first gate driving signal and the second gate driving signal. The apparatus and method is capable of reducing the complexity in design of the display circuit, which is advantageous for raising density of pixels of the display panel. The apparatus and method are applicable to manufacture a display.
-
公开(公告)号：US20170162095A1
公开(公告)日：2017-06-08
申请号：US15322543
申请日：2016-04-08
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chen Song , Zhongyuan Wu , Hongjun Xie , Kun Cao
CPC classification number: G09G3/20 , G09G3/3233 , G09G3/3266 , G09G2300/0408 , G09G2300/0842 , G09G2300/0861 , G09G2310/0286 , G09G2310/08 , G11C19/28
Abstract: Embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a display device. The shift register unit comprises two reset-set RS flip-flops. An set S terminal of a first RS flip-flop receives a trigger signal, and a reset R terminal of the first RS flip-flop receives a clock signal. An S terminal of a second RS terminal receives the clock signal, a R terminal of the second RS flip-flop is connected to a Q terminal of the first RS flip-flop, and a Q terminal of the second RS flip-flop is an output terminal of the shift register unit.
-
Patent Agency Ranking
公开(公告)号：US09536469B2
公开(公告)日：2017-01-03
申请号：US14769068
申请日：2015-01-06
Applicant: BOE TECHNOLOGY GROUP CO., LTD
IPC: G09G3/3225 , G09G3/32
CPC classification number: G09G3/3225 , G09G3/3266 , G09G2300/0809 , G09G2310/0213 , G09G2310/0218
Abstract: Disclosed is a pulse signal combination circuit for combining N input pulse signals sequentially effective within each display period into an output pulse signal, N being an integer greater than 1, including N output control units and a pulse signal output end. A first control end of an nth output control unit is configured to receive an nth input pulse signal, a second control end thereof is configured to receive an (n+1)th input pulse signal, and an output end thereof is connected to the pulse signal output end. The nth output control unit is configured to, within a time duration of each display period after the nth input pulse signal is effective for the first time and before the (n+1)th input pulse signal is effective for the first time, output the nth input pulse signal to the pulse signal output end, where n is a positive integer less than N.
Abstract translation: 公开了一种脉冲信号组合电路，用于将在每个显示周期内顺序有效的N个输入脉冲信号组合成输出脉冲信号，N是大于1的整数，包括N个输出控制单元和脉冲信号输出端。 第n输出控制单元的第一控制端被配置为接收第n输入脉冲信号，其第二控制端被配置为接收第（n + 1）个输入脉冲信号，并且其输出端连接到脉冲 信号输出端。 第n输出控制单元被配置为在第n个输入脉冲信号在第一次有效之后且在第（n + 1）个输入脉冲信号第一次有效之前的每个显示周期的持续时间内，输出 第n个输入脉冲信号到脉冲信号输出端，其中n是小于N的正整数。
-
公开(公告)号：US20160189677A1
公开(公告)日：2016-06-30
申请号：US14787893
申请日：2015-04-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： KUN CAO , Zhongyuan Wu , Chen Song
IPC: G09G5/10
CPC classification number: G09G5/10 , G09G3/3258 , G09G3/3266 , G09G2300/0408 , G09G2310/0262 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/043 , G09G2320/045 , G09G2330/021 , G09G2330/10 , G09G2330/12 , G11C19/287
Abstract: A display circuit and a driving method thereof and a display apparatus are provided. The display circuit comprises a pixel unit (11), a first gate driving unit (12) and a second gate driving unit (13); wherein the first gate driving unit (12) is configured to input a first gate driving signal to the pixel unit (11); the second gate driving unit (13) is configured to input a second gate driving signal to the pixel unit (11); and the pixel unit (11) is configured to perform threshold compensating and gray scale displaying simultaneously under the control of the first gate driving signal and the second gate driving signal. The apparatus and method is capable of reducing the complexity in design of the display circuit, which is advantageous for raising density of pixels of the display panel. The apparatus and method are applicable to manufacture a display.
Abstract translation: 提供了显示电路及其驱动方法和显示装置。 显示电路包括像素单元（11），第一栅极驱动单元（12）和第二栅极驱动单元（13）; 其中，所述第一栅极驱动单元（12）被配置为向所述像素单元（11）输入第一栅极驱动信号; 第二栅极驱动单元（13）被配置为将第二栅极驱动信号输入到像素单元（11）; 并且像素单元（11）被配置为在第一栅极驱动信号和第二栅极驱动信号的控制下同时进行阈值补偿和灰度显示。 该装置和方法能够降低显示电路的设计复杂度，这有利于提高显示面板的像素的密度。 该装置和方法适用于制造显示器。
-
公开(公告)号：US11323127B2
公开(公告)日：2022-05-03
申请号：US16607832
申请日：2019-04-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Tangxiang Wang , Chen Song
Abstract: A digital-to-analog conversion circuit, a digital-to-analog conversion method, and a display device are provided. The digital-to-analog conversion circuit includes a first digital-to-analog conversion sub-circuit and a second digital-to-analog conversion sub-circuit. The second digital-to-analog conversion sub-circuit includes least-significant-bit voltage selection modules whose quantity is a, a weighed summation operational amplifier, switching control modules whose quantity is a and energy storage modules whose quantity is a. The weighted summation operational amplifier includes a reverse-phase input end, an operational amplification output end, and same-phase input ends whose quantity is a. The reverse-phase input end is connected to the operational amplification output end, and a is an integer greater than 1. The weighted summation operational amplifier is configured to perform weighted summation on voltages inputted by the a same-phase input ends at a digital-to-analog conversion stage to acquire an analog voltage, and output the analog voltage via the operational amplification output end.
-
19.发明授权公开(公告)号：US11296718B2
公开(公告)日：2022-04-05
申请号：US16766602
申请日：2019-12-16
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Tangxiang Wang , Chen Song
Abstract: Digital-to-analog conversion circuit, digital-to-analog conversion method, display apparatus are disclosed. Digital-to-analog conversion circuit may comprise: voltage dividing sub-circuit comprising M voltage dividing signal terminals; decoding sub-circuit comprising M input and output terminals, M input terminals electrically coupled to first to Mth voltage dividing signal terminals of voltage dividing sub-circuit respectively, decoding sub-circuit configured to receive digital signal and select one of M input terminals to be electrically connected with output terminal according to digital signal; amplification sub-circuit comprising input and output terminals, input terminal of amplification sub-circuit electrically coupled to output terminal of decoding sub-circuit, amplification sub-circuit configured to amplify signal at its input terminal, output analog gray-scale voltage at output terminal, voltage dividing signal at voltage dividing signal terminal is less than or equal to ½ of maximum load voltage at output terminal of digital-to-analog conversion circuit, amplification sub-circuit has amplification coefficient N greater than or equal to 2.
-
公开(公告)号：US10924099B2
公开(公告)日：2021-02-16
申请号：US16643241
申请日：2019-09-05
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Tangxiang Wang , Chen Song
Abstract: Embodiments of the present disclosure provide a comparator. The comparator includes a first current source circuit, a pre-amplifier circuit, an amplifier circuit, a comparison circuit, and an output circuit. The first current source circuit is configured to provide a first constant current to the pre-amplifier circuit. The pre-amplifier circuit is configured to amplify a first input signal into a first pre-amplified signal and amplify a second input signal into a second pre-amplified signal based on a first constant current. The amplifier circuit includes a current mirror and a load circuit. The load circuit comprises a differential diode-connected transistor. The comparison circuit is configured to compare the first amplified signal with the second amplified signal. The output circuit is configured to output a first voltage or a second voltage based on a result of the comparison.
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.02 seconds)
