公开(公告)号：US20190097622A1

公开(公告)日：2019-03-28

申请号：US15717276

申请日：2017-09-27

申请人： Apple Inc.

发明人： Jaroslav Raszka ,  Amrinder S. Barn ,  Victor Zyuban ,  Shingo Suzuki ,  Ajay Kumar Bhatia ,  Mohamed H. Abu-Rahma ,  Shahzad Nazar ,  Greg M. Hess

IPC分类号： H03K17/16

CPC分类号： H03K17/162 ,  H03K17/145 ,  H03K19/0016 ,  H03K19/00369 ,  H03K2217/0027 ,  H03K2217/0036

摘要： A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

公开(公告)号：US09817937B2

公开(公告)日：2017-11-14

申请号：US14880420

申请日：2015-10-12

申请人： Apple Inc.

发明人： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

公开(公告)号：US09337825B2

公开(公告)日：2016-05-10

申请号：US14308886

申请日：2014-06-19

申请人： Apple Inc.

发明人： Toshinari Takayanagi ,  Shingo Suzuki

IPC分类号： H03K17/28 ,  H03K17/284 ,  H03K17/16 ,  H03K19/00 ,  H03K19/003 ,  H03K17/0412

CPC分类号： H03K17/284 ,  H03K17/0412 ,  H03K17/04206 ,  H03K17/164 ,  H03K19/0016 ,  H03K19/00361 ,  Y10T307/858

摘要： A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

公开(公告)号：US08779836B2

公开(公告)日：2014-07-15

申请号：US13972577

申请日：2013-08-21

申请人： Apple Inc.

发明人： Toshinari Takayanagi ,  Shingo Suzuki

IPC分类号： H03K17/296

CPC分类号： H03K17/284 ,  H03K17/0412 ,  H03K17/04206 ,  H03K17/164 ,  H03K19/0016 ,  H03K19/00361 ,  Y10T307/858

摘要： A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

摘要翻译： 公开了一种在唤醒期间用于电源开关加速方案的装置。 在一个实施例中，集成电路包括至少一个电源门控电路块。 电源门控电路块包括一个虚拟电压节点，当有效时，电压被提供给块的电路。 电源开关耦合在虚拟电压节点和相应的全局电压节点之间。 当电源门控电路块通电时，电源开关被顺序激活。 电源开关激活的速率随着虚拟电压节点上的电压的增加而增加。 顺序地激活功率开关可以防止电流涌入电源门控电路块中的过多电流。 当虚拟电压节点上的电压至少处于一定水平时，功率开关被激活的速率的增加可以允许更快的唤醒。

公开(公告)号：US20160241240A1

公开(公告)日：2016-08-18

申请号：US14622111

申请日：2015-02-13

申请人： Apple Inc.

发明人： Shingo Suzuki ,  Harsha Krishnamurthy ,  Edvin Catovic ,  Rajat Goel ,  Manoj Gopalan

IPC分类号： H03K19/003 ,  H03K19/00

CPC分类号： H03K19/00361 ,  H03K19/0013 ,  H03K19/0016

摘要： In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

摘要翻译： 在一个实施例中，集成电路可以包括一个或多个电源门控块和功率管理器电路。 功率管理器电路可以被配置为为每个电源门控块和块使能时钟生成块使能。 电源门控块可以在电源门控块中产生各种电源开关段的本地块使能。 特别地，电源门控块可以包括从电源管理器电路接收块使能的一组串联的触发器。 功率门控块可以包括为每个功率开关段提供本地块使能的一组多路复用器（多路复用器）。 多路复用器的一个输入耦合到块使能，另一个输入耦合到通过其它功率开关段之一传播的另一个功能。 因此，可以控制多路复用器来选择传播的使能或输入块使能。

公开(公告)号：US08726216B2

公开(公告)日：2014-05-13

申请号：US13628581

申请日：2012-09-27

申请人： Apple Inc.

发明人： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

摘要翻译： 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。

公开(公告)号：US20140089883A1

公开(公告)日：2014-03-27

申请号：US13628581

申请日：2012-09-27

申请人： APPLE INC.

发明人： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

摘要翻译： 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。

公开(公告)号：US20130335133A1

公开(公告)日：2013-12-19

申请号：US13972577

申请日：2013-08-21

申请人： Apple Inc.

发明人： Toshinari Takayanagi ,  Shingo Suzuki

IPC分类号： H03K17/0412

CPC分类号： H03K17/284 ,  H03K17/0412 ,  H03K17/04206 ,  H03K17/164 ,  H03K19/0016 ,  H03K19/00361 ,  Y10T307/858

摘要： A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.