公开(公告)号：US09524011B2

公开(公告)日：2016-12-20

申请号：US14251508

申请日：2014-04-11

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Michael L. Karm ,  Ian D. Kountanis ,  David J. Williamson

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/00 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

Abstract: Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).

Abstract translation: 公开了在执行指令循环期间降低功率的技术。 处理器可以使用多种不同的功率节省模式，例如在更多数量的循环迭代之后仅仅几次循环迭代（例如2-3）和第二更深的省电模式之后的第一省电模式。 第一省电模式可以包括保持分支预测器和/或其他结构是有效的，但是第二省电模式可以包括降低分支预测器和/或其他结构的功率。 在进入用于循环执行的省电模式之前，处理器还可以使用观察模式和指令捕获模式。 在执行具有多个后向分支（例如，嵌套循环）的复杂环路时也可以实现节电模式。