公开(公告)号：US11989640B2

公开(公告)日：2024-05-21

申请号：US17991373

申请日：2022-11-21

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20230088591A1

公开(公告)日：2023-03-23

申请号：US17932177

申请日：2022-09-14

Applicant: Apple Inc.

Inventor： Fernando A. Mujica ,  Joyce Y. Kwong ,  Mark P. Colosky

IPC: G05B23/02

Abstract: Fault tolerance for an automation controller for a machine is provided. A first portion of phases of the automation controller may be processed with fail operational protection, in which a failure of one of the computers used for the first portion still permits full operational functionality in the machine. The remaining portion of the phases are processed with fail degraded protection, in which a failure of a computer used for the remaining portion permits continued operation but with one or more constraints, as compared to the fail operational portions.

公开(公告)号：US11537838B2

公开(公告)日：2022-12-27

申请号：US15971882

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Erik K. Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20190190854A1

公开(公告)日：2019-06-20

申请号：US16282190

申请日：2019-02-21

Applicant: Apple Inc.

Inventor： Fernando A. Mujica ,  Joyce Y. Kwong ,  Leland W. Lew

IPC: H04L12/939 ,  H04L12/707 ,  H04L12/24 ,  H04L12/825

CPC classification number: H04L49/552 ,  H04L41/0659 ,  H04L41/0672 ,  H04L45/24 ,  H04L47/25

Abstract: Data generated by one or more data producers may be transmitted via multiple communication paths according to a path transmission scheme that divides transmission of different portions of the data amongst different communication paths. Upon a failure of a communication path, transmission of data may continue for those portions of data that are not assigned to the failed communication path. In some embodiments, modifications to the path transmission scheme may be made to change the division of data amongst remaining communication paths in the event of failure.