公开(公告)号：US20170185514A1

公开(公告)日：2017-06-29

申请号：US14981833

申请日：2015-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Blinzer ,  Ali Ibrahim ,  Benjamin T. Sander ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F9/46

Abstract: A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.

公开(公告)号：US20160092181A1

公开(公告)日：2016-03-31

申请号：US14501296

申请日：2014-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory P. Rodgers ,  Benjamin T. Sander ,  Shreyas Ramalingam

IPC: G06F9/45

CPC classification number: G06F8/447

Abstract: A programming model for a processor accelerator allows accelerated functions to be called from a main program directly without a management API for the accelerator. A compiler automatically generates wrapper source code for each accelerator function called by the application source code. The wrapper code is compiled, together with the accelerator source code, to generate an object file that is linked to an object file for the main program. By automatically generating the wrapper code, a programmer can simply and directly invoke accelerator functions without the use of a complex management API. In addition, because the wrapper code for the accelerator is generated automatically, a standard compiler can be used to compile the main program, using standard linkage conventions.

Abstract translation: 处理器加速器的编程模型允许从主程序直接调用加速函数，而不需要加速器的管理API。 编译器自动为应用程序源代码调用的每个加速器函数生成包装器源代码。 包装器代码与加速器源代码一起编译，以生成链接到主程序的对象文件的对象文件。 通过自动生成包装代码，程序员可以简单直接地调用加速器功能，而无需使用复杂的管理API。 另外，由于加速器的包装代码是自动生成的，因此可以使用标准编译器来编译主程序，使用标准的链接约定。

公开(公告)号：US11288205B2

公开(公告)日：2022-03-29

申请号：US14747980

申请日：2015-06-23

Applicant: Avanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Mike Mantor

IPC: G06F12/1027 ,  G06F12/0893

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US20160378682A1

公开(公告)日：2016-12-29

申请号：US14747980

申请日：2015-06-23

Applicant: Avanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Mike Mantor

IPC: G06F12/10 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F12/0893 ,  G06F2212/684

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

Abstract translation: 处理器在处理器的高速缓存中维护指示高速缓存未命中流的访问日志。 响应于高速缓存的高速缓存未命中的至少一个子集中的每一个，处理器在访问日志中记录相应的条目，指示导致相应的未命中的存储器访问请求的物理存储器地址。 此外，处理器维护地址转换日志，其指示物理存储器地址与虚拟存储器地址的映射。 响应于将虚拟地址转换为物理地址的地址转换（例如，寻路步行），处理器在地址转换日志的条目处存储物理地址与对应的虚拟地址的映射。 处理器执行的软件可以使用两个日志进行内存管理。