公开(公告)号：US20170185514A1

公开(公告)日：2017-06-29

申请号：US14981833

申请日：2015-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Blinzer ,  Ali Ibrahim ,  Benjamin T. Sander ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F9/46

Abstract: A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.

公开(公告)号：US10467138B2

公开(公告)日：2019-11-05

申请号：US14981833

申请日：2015-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Blinzer ,  Ali Ibrahim ,  Benjamin T. Sander ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0888 ,  G06F12/0815 ,  G06F12/0813 ,  H04L29/08

Abstract: A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.