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11.发明授权公开(公告)号：US11079831B2
公开(公告)日：2021-08-03
申请号：US16363762
申请日：2019-03-25
Applicant: Apple Inc.
Inventor： Toshinari Takayanagi , Jung Wook Cho , Patrick D. McNamara
IPC: G06F1/324 , G06F1/26 , G06F1/3296
Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.
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公开(公告)号：US20160291625A1
公开(公告)日：2016-10-06
申请号：US14673326
申请日：2015-03-30
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Eric G. Smith , Erik P. Machnicki , Jung Wook Cho , Khaled M. Alashmouny , Kiran B. Kattel , Vijay M. Bettada , Bo Yang , Wenlong Wei
IPC: G05F3/02
CPC classification number: G05F3/02 , G06F1/324 , G06F1/3296
Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.
Abstract translation: 公开了一种欠压检测电路及其运算方法。 在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。 逻辑电路被耦合以从第一和第二比较器接收信号。 在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。 提供给功能电路的时钟信号可以响应于指示而被节流。 如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。
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13.发明申请System on a Chip with Always-On Processor Which Reconfigures SOC and Supports Memory-Only Communication Mode 有权使用永久处理器的芯片上的系统重新配置SOC并支持仅内存通信模式公开(公告)号：US20150347287A1
公开(公告)日：2015-12-03
申请号：US14458949
申请日：2014-08-13
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. De Cesare , Anand Dalal
CPC classification number: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。
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14.发明申请CONTROL SCHEME TO TEMPORARILY RAISE SUPPLY VOLTAGE IN RESPONSE TO SUDDEN CHANGE IN CURRENT DEMAND 有权针对当前需求改变的响应中的电力供应电压控制方案公开(公告)号：US20140380066A1
公开(公告)日：2014-12-25
申请号：US13925950
申请日：2013-06-25
Applicant: Apple Inc.
Inventor： Toshinari Takayanagi , Jung Wook Cho , Patrick D. McNamara
IPC: G06F1/26
CPC classification number: G06F1/324 , G06F1/26 , G06F1/266 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.
Abstract translation: 一种用于管理当前需求的变化的系统，包括一个或多个处理器，耦合到至少一个处理器的存储器，时钟生成电路，其耦合到存储器并被配置为输出时钟，一个或多个功能块，电源 ，被配置为输出多个电压电平，以及电源管理单元。 功率管理单元可以被配置为将电源输出设置为第一电压电平，然后检测SoC内当前需求即将发生变化的指示。 如果检测到当前需求即将发生变化的指示，则电源管理单元可以被配置为将电源输出调整到第二电压电平。 在确定了当前需求即将发生变化之后，电源管理单元可被配置为将电源输出调整回到第一电压电平。
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15.发明授权Hardware automatic performance state transitions in system on processor sleep and wake events 有权系统中处理器睡眠和唤醒事件的硬件自动性能状态转换公开(公告)号：US08656196B2
公开(公告)日：2014-02-18
申请号：US13863554
申请日：2013-04-16
Applicant: Apple Inc.
Inventor： Josh P. de Cesare , Jung Wook Cho , Toshinari Takayanagi , Timothy J. Millet
CPC classification number: G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。
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Patent Agency Ranking
16.发明申请Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events 有权处理器睡眠和唤醒事件的硬件自动性能状态转换系统公开(公告)号：US20130232364A1
公开(公告)日：2013-09-05
申请号：US13863554
申请日：2013-04-16
Applicant: APPLE INC.
Inventor： Josh P. de Cesare , Jung Wook Cho , Toshinari Takayanagi , Timothy J. Millet
IPC: G06F1/32
CPC classification number: G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。
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公开(公告)号：US12135602B2
公开(公告)日：2024-11-05
申请号：US17573268
申请日：2022-01-11
Applicant: Apple Inc.
Inventor： Doron Rajwan , Inder M. Sodhi , Keith Cox , Jung Wook Cho , Kevin I. Park , Tal Kuzi
IPC: G06F1/3296 , G06F1/3234 , G06F1/324
Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
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公开(公告)号：US20230101217A1
公开(公告)日：2023-03-30
申请号：US17573268
申请日：2022-01-11
Applicant: Apple Inc.
Inventor： Doron Rajwan , Inder M. Sodhi , Keith Cox , Jung Wook Cho , Kevin I. Park , Tal Kuzi
IPC: G06F1/3296 , G06F1/324 , G06F1/3234
Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
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19.发明申请公开(公告)号：US20170177256A1
公开(公告)日：2017-06-22
申请号：US15447328
申请日：2017-03-02
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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20.发明授权Control scheme to temporarily raise supply voltage in response to sudden change in current demand 有权针对当前需求突然变化暂时提高供电电压的控制方案公开(公告)号：US09395775B2
公开(公告)日：2016-07-19
申请号：US13925950
申请日：2013-06-25
Applicant: Apple Inc.
Inventor： Toshinari Takayanagi , Jung Wook Cho , Patrick D. McNamara
CPC classification number: G06F1/324 , G06F1/26 , G06F1/266 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.
Abstract translation: 一种用于管理当前需求的变化的系统，包括一个或多个处理器，耦合到至少一个处理器的存储器，时钟生成电路，其耦合到存储器并被配置为输出时钟，一个或多个功能块，电源 ，被配置为输出多个电压电平，以及电源管理单元。 功率管理单元可以被配置为将电源输出设置为第一电压电平，然后检测SoC内当前需求即将发生变化的指示。 如果检测到当前需求即将发生变化的指示，则电源管理单元可以被配置为将电源输出调整到第二电压电平。 在确定了当前需求即将发生变化之后，电源管理单元可被配置为将电源输出调整回到第一电压电平。
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