公开(公告)号：US20140089546A1

公开(公告)日：2014-03-27

申请号：US13629509

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Josh P. de Cesare ,  Manu Gulati

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.

Abstract translation: 一种用于保持精确中断时间戳的系统和方法。 半导体芯片包括具有多个中断源的接口的中断控制器（IC）。 响应于接收到中断，IC复制并记录存储在用于维持全局经过时间的主时基计数器中的值。 IC向对应的处理器发送中断指示。 中断服务程序（ISR）或设备驱动程序请求与中断相关联的时间戳。 处理器不是向操作系统发送请求以获得存储在主时基计数器中的当前值，而是从IC请求记录的时间戳。 IC识别与中断相关联的存储时间戳，并将其返回给处理器。

公开(公告)号：US20210333132A1

公开(公告)日：2021-10-28

申请号：US17366459

申请日：2021-07-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal ,  Michael F. Culbert

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US11079261B2

公开(公告)日：2021-08-03

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US20200149932A1

公开(公告)日：2020-05-14

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F1/3206 ,  G06F13/16

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US09639143B2

公开(公告)日：2017-05-02

申请号：US14876922

申请日：2015-10-07

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

公开(公告)号：US09529405B2

公开(公告)日：2016-12-27

申请号：US14459482

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gilbert H. Herbeck ,  Shu-Yi Yu ,  Sebastian Skalberg

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units.

Abstract translation: 公开了一种用于管理IC中的功能单元的空闲的系统和方法。 IC包括具有多个功能单元和空闲聚合单元的子系统。 当特定功能单元确定它是空闲时，它可以向空闲聚合单元断言空闲指示。 当对于所有功能单元同时断言相应的空闲指示时，空闲汇聚单元可以向每个功能单元断言并提供相应的空闲请求信号。 响应于接收空闲请求单元，如果没有事务进入，则给定功能单元可以向空闲聚合单元提供确认信号。 如果所有功能单元已经同时确定其各自的确认信号，则空闲聚合单元可以向时钟选通单元提供相同的指示，时钟门控单元然后可以对由功能单元接收的时钟信号进行门控。

公开(公告)号：US20150326216A1

公开(公告)日：2015-11-12

申请号：US14275473

申请日：2014-05-12

Applicant: Apple Inc.

Inventor： Erik P. Machnicki

IPC: H03K17/14 ,  G05B13/02

CPC classification number: H03K19/00369 ,  G05B13/021 ,  H03K17/14 ,  Y10T307/773

Abstract: A method and apparatus for thermal voltage margin recovery is disclosed. In one embodiment, an integrated circuit (IC) includes first and second temperature sensors at first and second locations of the IC, respectively. The IC further includes a power management circuit coupled to receive temperature readings from the first and second temperature sensors. Based on received temperature readings, the power management circuit may determine a voltage offset value. The power management circuit may then reduce the operating voltage of the IC by the voltage offset value.

Abstract translation: 公开了一种用于热电压裕度恢复的方法和装置。 在一个实施例中，集成电路（IC）分别在IC的第一和第二位置处包括第一和第二温度传感器。 IC还包括电源管理电路，其耦合以接收来自第一和第二温度传感器的温度读数。 基于所接收的温度读数，功率管理电路可以确定电压偏移值。 然后，电源管理电路可以通过电压偏移值来降低IC的工作电压。

公开(公告)号：US08963587B2

公开(公告)日：2015-02-24

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K21/00

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。

公开(公告)号：US20140340130A1

公开(公告)日：2014-11-20

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K3/02

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。

公开(公告)号：US08867533B2

公开(公告)日：2014-10-21

申请号：US13736462

申请日：2013-01-08

Applicant: Apple Inc.

Inventor： Erik P. Machnicki

IPC: H04L12/66 ,  H04L12/50 ,  H04J3/02 ,  G06F15/173 ,  H04L12/933

CPC classification number: H04L49/254 ,  H04L49/10

Abstract: Systems and methods for arbitrating among traffic from a coherence point to a switch fabric. A multi-level arbiter is used to avoid starvation while providing fairness and high bandwidth on the connection path between the coherence point and the switch fabric. A first level of arbitration selects packets with enough available credits for forwarding from the switch fabric on a downstream channel. The second level of arbitration arbitrates among short packets at a first arbiter and arbitrates among long packets at a second arbiter. The selected short packet and the selected long packet are forwarded to a third level of arbitration. The third level of arbitration alternates between long and short packets and forwards the selected packet to the switch fabric.

Abstract translation: 从相干点到交换结构的流量之间的仲裁的系统和方法。 多级仲裁器用于避免饥饿，同时在相干点和交换结构之间的连接路径上提供公平性和高带宽。 第一级仲裁选择具有足够可用信用的分组，用于从下游信道上的交换结构转发。 第二级仲裁在第一仲裁器的短分组之间进行仲裁，并在第二仲裁器的长分组之间进行仲裁。 所选择的短分组和所选择的长分组被转发到第三级仲裁。 第三级仲裁在长数据包和短数据包之间交替转发，并将所选数据包转发给交换结构。