公开(公告)号：US20210334098A1

公开(公告)日：2021-10-28

申请号：US16856832

申请日：2020-04-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Marko Scrbak ,  Mahzabeen Islam ,  John Kalamatianos ,  Jagadish B. Kotra

IPC: G06F9/26 ,  G06F9/38 ,  G06F12/0893 ,  G06F16/901

Abstract: A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.

公开(公告)号：US12153524B2

公开(公告)日：2024-11-26

申请号：US17957358

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Marko Scrbak ,  Gabriel H. Loh ,  Akhil Arunkumar

IPC: G06F12/0862

Abstract: A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US12099723B2

公开(公告)日：2024-09-24

申请号：US17956614

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Marko Scrbak

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. The method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored across the multiple grains of the plurality of grains.

公开(公告)号：US12019566B2

公开(公告)日：2024-06-25

申请号：US16938364

申请日：2020-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sergey Blagodurov ,  Johnathan Alsop ,  Jagadish B. Kotra ,  Marko Scrbak ,  Ganesh Dasika

IPC: G06F13/16 ,  G06F9/30 ,  H04L45/122

CPC classification number: G06F13/1642 ,  G06F9/3004 ,  G06F9/30098 ,  G06F13/1663 ,  H04L45/122

Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.

公开(公告)号：US20240111676A1

公开(公告)日：2024-04-04

申请号：US17957358

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Marko Scrbak ,  Gabriel H. Loh ,  Akhil Arunkumar

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6028

Abstract: A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US11914517B2

公开(公告)日：2024-02-27

申请号：US17094989

申请日：2020-11-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Marko Scrbak ,  Brandon K. Potter

IPC: G06F12/08 ,  G06F12/0877 ,  G06F12/0815

CPC classification number: G06F12/0877 ,  G06F12/0815 ,  G06F2212/621

Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.

公开(公告)号：US20230359556A1

公开(公告)日：2023-11-09

申请号：US17735469

申请日：2022-05-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Marko Scrbak

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: An electronic device includes a processor and a memory separate from the processor. The memory includes memory circuitry including a plurality of locations and processor in memory circuitry. In some implementations, some or all of the locations are used for storing cache blocks for a cache memory and the processor in memory circuitry performs operations for handling cache blocks in the memory circuitry. In some implementations, some or all of the locations are used for storing data for a memory and the processor in memory circuitry performs operations for handling data in the memory circuitry.

公开(公告)号：US11681620B2

公开(公告)日：2023-06-20

申请号：US17384420

申请日：2021-07-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Marko Scrbak ,  Jagadish Kotra

IPC: G06F12/0808 ,  G06F11/10

CPC classification number: G06F12/0808 ,  G06F11/1064 ,  G06F2212/1044

Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.