公开(公告)号：US20230022320A1

公开(公告)日：2023-01-26

申请号：US17384420

申请日：2021-07-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Marko Scrbak ,  Jagadish Kotra

IPC: G06F12/0808 ,  G06F11/10

Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.

公开(公告)号：US11481331B2

公开(公告)日：2022-10-25

申请号：US17135832

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish Kotra ,  John Kalamatianos

IPC: G06F12/0862

Abstract: An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

公开(公告)号：US20220261350A1

公开(公告)日：2022-08-18

申请号：US17730754

申请日：2022-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish Kotra ,  John Kalamatianos

IPC: G06F12/0862

Abstract: An electronic device includes a processor, the processor having a cache memory, a set of physical registers, and a promotion logic functional block. When one or more promotion conditions are met, the promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory to a physical register among the set of physical registers. For promoting the prefetched data, the promotion logic functional block acquires the prefetched data from the portion of the cache block and stores the prefetched data in the physical register

公开(公告)号：US11681620B2

公开(公告)日：2023-06-20

申请号：US17384420

申请日：2021-07-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Marko Scrbak ,  Jagadish Kotra

IPC: G06F12/0808 ,  G06F11/10

CPC classification number: G06F12/0808 ,  G06F11/1064 ,  G06F2212/1044

Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.

公开(公告)号：US20220100665A1

公开(公告)日：2022-03-31

申请号：US17135832

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish Kotra ,  John Kalamatianos

IPC: G06F12/0862

Abstract: An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.