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    Defect detection recipe definition
    11.
    发明授权
    Defect detection recipe definition 有权
    缺陷检测配方定义

    公开(公告)号：US08289508B2

    公开(公告)日：2012-10-16

    申请号：US12621510

    申请日：2009-11-19

    Applicant: Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

    Inventor： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

    IPC: G01N21/00

    CPC classification number: H01L22/12

    Abstract: A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.

    Abstract translation: 公开了一种形成装置的方法。 该方法包括提供衬底并在衬底上处理器件的一层。 该层用检查工具检查缺陷。 检查工具用从在已知位置处编程到层中的缺陷来确定的检查配方来编程。

    STI scheme to prevent fox recess during pre-CMP HF dip
    13.
    发明授权
    STI scheme to prevent fox recess during pre-CMP HF dip 失效
    STI方案，以防止在前CMP HF浸渍期间的狐狸凹陷

    公开(公告)号：US06673695B1

    公开(公告)日：2004-01-06

    申请号：US10062657

    申请日：2002-02-01

    Applicant: Victor Seng-Keong Lim ,  Paul Proctor

    Inventor： Victor Seng-Keong Lim ,  Paul Proctor

    IPC: H01L2176

    CPC classification number: H01L21/76229 ,  H01L21/76224

    Abstract: A new method is provided for the creation of STI regions. STI trenches are created in the surface of a substrate following conventional processing. A layer of STI oxide is deposited and, using an exposure mask that is a reverse mask of the mask that is used to create the STI pattern, impurity implants are performed into the surface of the deposited layer of STI oxide. In view of these processing conditions, the layer of STI oxide overlying the patterned layer of etch stop material is exposed to the impurity implants. This exposure alters the etch characteristics of the deposited layer of STI oxide where this STI oxide overlies the patterned layer of etch stop material. The etch rate of the impurity exposed STI oxide is increased by the impurity implantation, resulting in an etch overlying the patterned etch stop layer that proceeds considerably faster than the etch of the STI oxide that is deposited overlying the created STI trenches. With the significantly faster etch of the STI oxide where this oxide has been exposed to impurity implantation, the STI oxide removal can be equalized between the STI oxide that overlies the patterned etch stop layer and the oxide that has been deposited over the STI trenches.

    Abstract translation: 为创建STI区域提供了一种新方法。 在常规处理之后，在衬底的表面中产生STI沟槽。 沉积一层STI氧化物，并且使用作为用于产生STI图案的掩模的反掩模的曝光掩模，将杂质植入物进行到STI氧化物沉积层的表面。 鉴于这些处理条件，覆盖图案化的蚀刻停止材料层的STI氧化物层暴露于杂质注入。 该曝光改变STI氧化物沉积层的蚀刻特性，其中该STI氧化物覆盖在图案化的蚀刻停止材料层上。 通过杂质注入，杂质暴露的STI氧化物的蚀刻速率增加，导致覆盖图案化的蚀刻停止层的蚀刻显着快于沉积在所创建的STI沟槽上的STI氧化物的蚀刻。 通过对这种氧化物暴露于杂质注入的STI氧化物的显着更快的蚀刻，可以在覆盖图案化蚀刻停止层的STI氧化物和已经沉积在STI沟槽上的氧化物之间均衡STI氧化物去除。

    Multiple step CMP polishing
    16.
    发明授权
    Multiple step CMP polishing 失效

    公开(公告)号：US06663472B2

    公开(公告)日：2003-12-16

    申请号：US10062656

    申请日：2002-02-01

    Applicant: Victor Seng-Keong Lim ,  Chen Feng ,  Subramanian Balakumar ,  Paul Proctor

    Inventor： Victor Seng-Keong Lim ,  Chen Feng ,  Subramanian Balakumar ,  Paul Proctor

    IPC: B24B508

    CPC classification number: B24B37/26 ,  B24B57/02

    Abstract: An improved chemical mechanical polishing apparatus for planarizing semiconductor surface materials. The single rotating polishing platen with an attached pad of conventional CMP processes is replaced with two controlled independently driven, concentric and coplanar, polishing platens. The two co-planar polishing platens allows for separate adjustable options to the CMP polishing process. The options are provided by having pads of different material compositions and hardness. Moreover, an annular space is provided between the platens to introduce the usage of two slurry formulations, one to each pad, on the same CMP tool. The annular space between platens forming a drain path for catching and containing slurry waste.

    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
    17.
    发明授权
    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 有权

    公开(公告)号：US06472697B2

    公开(公告)日：2002-10-29

    申请号：US10140574

    申请日：2002-05-08

    Applicant: Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    Inventor： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    IPC: H01L2710

    CPC classification number: H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
    18.
    发明授权
    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 失效

    公开(公告)号：US06399471B1

    公开(公告)日：2002-06-04

    申请号：US09783379

    申请日：2001-02-15

    Applicant: Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    Inventor： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    IPC: H01L2144

    CPC classification number: H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

    E-BEAM INSPECTION STRUCTURE FOR LEAKAGE ANALYSIS
    19.
    发明申请
    E-BEAM INSPECTION STRUCTURE FOR LEAKAGE ANALYSIS 有权
    用于泄漏分析的电子束检查结构

    公开(公告)号：US20090057664A1

    公开(公告)日：2009-03-05

    申请号：US11845787

    申请日：2007-08-28

    Applicant: Victor Seng Keong LIM ,  Jeffrey LAM

    Inventor： Victor Seng Keong LIM ,  Jeffrey LAM

    IPC: H01L23/58 ,  G01N23/00 ,  G01R31/26

    CPC classification number: H01L22/34 ,  G01R31/2884 ,  G01R31/307

    Abstract: A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/ one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.

    Abstract translation: 测试结构和使用测试结构的方法，其中测试结构由八个测试结构中的至少一个组成，当电压对比度扫描具有至少一个预定的结构缺陷时，其具有可辨别的缺陷特征。 八个测试结构为：1）具有有源面积（AA）/ P-N结泄漏; 2）具有对地的隔离区域; 3）具有AA / P-N结和隔离区; 4）具有栅极电介质泄漏和栅极到隔离区域对地; 5）具有通过AA / P-N结到漏电的栅极电介质泄漏; 6）具有栅极电介质接地和栅极/一侧隔离区域泄漏到地面; 7）具有通过AA / P-N结到接地漏电的超大栅极电介质; 和8）具有AA / P-N结泄漏栅介质泄漏。

    Method to achieve STI planarization
    20.
    发明授权
    Method to achieve STI planarization 失效
    实现STI平坦化的方法

    公开(公告)号：US06403484B1

    公开(公告)日：2002-06-11

    申请号：US09803187

    申请日：2001-03-12

    Applicant: Victor Seng Keong Lim ,  Lap Chan ,  James Lee ,  Chen Feng ,  Wang Ling Goh

    Inventor： Victor Seng Keong Lim ,  Lap Chan ,  James Lee ,  Chen Feng ,  Wang Ling Goh

    IPC: H01L2100

    CPC classification number: H01L21/31056 ,  H01L21/31053 ,  H01L21/76229

    Abstract: A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.

    Abstract translation: 描述了形成浅沟槽隔离的方法。 通过第一蚀刻停止层将多个隔离沟槽蚀刻到下面的半导体衬底中。 使用高密度等离子体化学气相沉积工艺（HDP-CVD）在第一蚀刻停止层和隔离沟槽内沉积氧化物层，其中在氧化物层填充隔离沟槽之后，沉积组分被中断，同时继续溅射组分 直到第一蚀刻停止层的角部暴露在隔离沟槽的边缘处，由此隔离沟槽内的氧化物层与覆盖在第一蚀刻停止层上的氧化物层断开。 此后，沉积在隔离沟槽内的氧化物层上的第二蚀刻停止层，覆盖在第一蚀刻停止层上的氧化物层和暴露的第一蚀刻停止层拐角。 将第二蚀刻停止层抛光，直到暴露出覆盖在第一蚀刻停止层上的氧化物层。 去除覆盖在第一蚀刻停止层上的暴露的氧化物层。 去除第一和第二蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区。

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