公开(公告)号：US08088668B2

公开(公告)日：2012-01-03

申请号：US12700088

申请日：2010-02-04

Applicant: Shin Bin Huang ,  Chung-Yi Chang ,  Jung-Hung Wang

Inventor： Shin Bin Huang ,  Chung-Yi Chang ,  Jung-Hung Wang

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.

Abstract translation: 用于制造半导体存储器的电容器下电极的方法首先在具有多个导电插塞的半导体衬底上形成第一层叠结构。 然后在第一堆叠结构上形成第二堆叠结构; 此外，形成从第二堆叠结构的顶表面延伸到第一堆叠结构的底表面的多个沟槽，并暴露导电插头; 最后，导电金属材料和固体导电圆柱形结构依次沉积在沟槽中，并且导电金属材料与导电插塞和导电圆柱形结构接触。 每个导电圆柱形结构是电容器下电极。 因此，本发明可以增加电容器下电极的支撑应力，并且进一步降低了在电容器下电极之外设置电容器上电极和电容器电介质层的难度。

公开(公告)号：US08003480B2

公开(公告)日：2011-08-23

申请号：US12700796

申请日：2010-02-05

Applicant: Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer.

Abstract translation: 公开了一种使用氧化物载体制造微米堆叠DRAM的电容器下电极的方法。 首先，形成堆叠结构。 其次，在上部氧化物层上形成光致抗蚀剂层，然后蚀刻它们。 第三，将多晶硅层沉积到上氧化物层和氮化物层上。 第四，在多晶硅层和上部氧化物层上沉积氮氧化物层。 第六，部分地蚀刻氮氧化物层，多晶硅层和上部氧化物层以形成多个通孔。 第七，氧化多晶硅层以形成围绕通孔的多个二氧化硅。 第八，在通孔下方蚀刻氮化物层，介电层和低氧化物层。 第九，在每个通孔中形成金属板和电容器下电极。 第十，蚀刻氮氧化物层，多晶硅层，氮化物层和电介质层。

公开(公告)号：US20110076828A1

公开(公告)日：2011-03-31

申请号：US12700088

申请日：2010-02-04

Applicant: SHIN BIN HUANG ,  CHUNG-YI CHANG ,  JUNG-HUNG WANG

Inventor： SHIN BIN HUANG ,  CHUNG-YI CHANG ,  JUNG-HUNG WANG

IPC: H01L21/02

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.

Abstract translation: 用于制造半导体存储器的电容器下电极的方法首先在具有多个导电插塞的半导体衬底上形成第一层叠结构。 然后在第一堆叠结构上形成第二堆叠结构; 此外，形成从第二堆叠结构的顶表面延伸到第一堆叠结构的底表面的多个沟槽，并暴露导电插头; 最后，导电金属材料和固体导电圆柱形结构依次沉积在沟槽中，并且导电金属材料与导电插塞和导电圆柱形结构接触。 每个导电圆柱形结构是电容器下电极。 因此，本发明可以增加电容器下电极的支撑应力，并且进一步降低了在电容器下电极之外设置电容器上电极和电容器电介质层的难度。

公开(公告)号：US20090040823A1

公开(公告)日：2009-02-12

申请号：US11946872

申请日：2007-11-29

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: G11C16/04

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash memory. The sawtooth gate conductor line results in select gate transistors having different select gate lengths and produces at least one depletion-mode select transistor at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract translation: 提供闪存。 提供了将布置在同一列上的选择栅极晶体管的选通栅极互连的锯齿波导线。 设置在存储单元串的两个远端上的锯齿形栅极导线增加了闪速存储器的集成。 锯齿波导线导致选择栅极晶体管具有不同的选择栅极长度，并在存储单元串的一侧产生至少一个耗尽型选择晶体管。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US20130252397A1

公开(公告)日：2013-09-26

申请号：US13476251

申请日：2012-05-21

Applicant: SHIN-BIN HUANG ,  CHENG-YEH HSU ,  CHUNG-LIN HUANG

Inventor： SHIN-BIN HUANG ,  CHENG-YEH HSU ,  CHUNG-LIN HUANG

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.

Abstract translation: 提供一种电容器结构的制造方法，其包括以下步骤：在具有第一氧化物层的衬底上，（a）在第一氧化物层上形成第一悬浮层; （b）在衬底上方的第一氧化物层中形成第一浅沟槽; （c）形成填充所述第一浅沟槽的第二氧化物层; （d）在第二氧化物层上形成第二悬浮层; （e）通过所述第二悬浮层形成穿过所述第一悬浮层上方的所述第二氧化物层的第二浅沟槽; （f）通过第二和第一氧化物层在第二浅沟槽的底表面上形成至少一个深沟槽，（g）在深沟槽的内表面上形成电极层; 和（h）通过第一和第二悬浮层中的沟槽开口去除第一和第二氧化物层。

公开(公告)号：US20110081763A1

公开(公告)日：2011-04-07

申请号：US12700796

申请日：2010-02-05

Applicant: SHIN BIN HUANG ,  CHING-NAN HSIAO ,  CHUNG-LIN HUANG

Inventor： SHIN BIN HUANG ,  CHING-NAN HSIAO ,  CHUNG-LIN HUANG

IPC: H01L21/02

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer.

Abstract translation: 公开了一种使用氧化物载体制造微米堆叠DRAM的电容器下电极的方法。 首先，形成堆叠结构。 其次，在上部氧化物层上形成光致抗蚀剂层，然后蚀刻它们。 第三，将多晶硅层沉积到上氧化物层和氮化物层上。 第四，在多晶硅层和上部氧化物层上沉积氮氧化物层。 第六，部分地蚀刻氮氧化物层，多晶硅层和上部氧化物层以形成多个通孔。 第七，氧化多晶硅层以形成围绕通孔的多个二氧化硅。 第八，在通孔下方蚀刻氮化物层，介电层和低氧化物层。 第九，在每个通孔中形成金属板和电容器下电极。 第十，蚀刻氮氧化物层，多晶硅层，氮化物层和电介质层。

公开(公告)号：US20110065253A1

公开(公告)日：2011-03-17

申请号：US12698322

申请日：2010-02-02

Applicant: SHIN-BIN HUANG ,  TSUNG-HAN LEE ,  CHUNG-LIN HUANG

Inventor： SHIN-BIN HUANG ,  TSUNG-HAN LEE ,  CHUNG-LIN HUANG

IPC: H01L21/02

CPC classification number: H01L27/10852 ,  H01L28/90

Abstract: A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.

Abstract translation: 堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

公开(公告)号：US08148766B2

公开(公告)日：2012-04-03

申请号：US12244295

申请日：2008-10-02

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

Abstract translation: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US20110092044A1

公开(公告)日：2011-04-21

申请号：US12699399

申请日：2010-02-03

Applicant: SHIN-BIN HUANG ,  TZUNG-HAN LEE ,  CHUNG-LIN HUANG

Inventor： SHIN-BIN HUANG ,  TZUNG-HAN LEE ,  CHUNG-LIN HUANG

IPC: H01L21/02

CPC classification number: H01L28/92

Abstract: A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer.

Abstract translation: 制造电容器下电极的方法包括电介质层，第一氮化硅层和硬掩模层; 部分地蚀刻硬掩模层，第一氮化硅层和电介质层以形成多个凹部; 在所述硬掩模层上沉积第二氮化硅层并进入所述凹部; 部分蚀刻第二氮化硅层，硬掩模层和电介质层以形成多个沟槽; 在每个沟槽内形成电容器下电极，并部分地蚀刻第一氮化硅层，第二氮化硅层，电介质层和电容器下电极以形成蚀刻区域; 并且从蚀刻区域蚀刻除去电介质层，由此每个电容器下电极的周围被第二氮化硅层包围并附着。

公开(公告)号：US20110086490A1

公开(公告)日：2011-04-14

申请号：US12720977

申请日：2010-03-10

Applicant: HSIAO-LEI WANG ,  SHIN BIN HUANG ,  CHING-NAN HSIAO ,  CHUNG-LIN HUANG

Inventor： HSIAO-LEI WANG ,  SHIN BIN HUANG ,  CHING-NAN HSIAO ,  CHUNG-LIN HUANG

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/31111 ,  H01L27/10852

Abstract: A single-side implanting process for capacitors of stack DRAM is disclosed. Firstly, form a stacked structure with a dielectric layer and an insulating nitride layer on a semi-conductor substrate and etch the stacked structure to form a plurality of trenches. Then, form conductive metal plates respectively on an upper surface of the stacked structure and bottoms of the trenches, form a continuous conductive nitride film, form a continuous oxide film, and form a photo resist layer for covering the trenches which are provided for isolation. Then, form a plurality of implanted oxide areas on a single-side surface, remove the photo resist layer, remove the plurality of implanted oxide areas, remove the conductive metal plates and the conductive nitride film uncovered by the oxide film, and remove the oxide film and the dielectric film.

Abstract translation: 公开了用于堆叠DRAM的电容器的单侧注入工艺。 首先，在半导体基板上形成具有介电层和绝缘氮化物层的堆叠结构，并蚀刻该层叠结构以形成多个沟槽。 然后，分别在层叠结构的上表面和沟槽的底部形成导电性金属板，形成连续的导电性氮化物膜，形成连续的氧化膜，形成用于覆盖设置用于隔离的沟槽的光致抗蚀剂层。 然后，在单面表面上形成多个注入的氧化物区域，去除光致抗蚀剂层，去除多个注入的氧化物区域，去除未被氧化膜覆盖的导电金属板和导电氮化物膜，并除去氧化物 薄膜和电介质薄膜。