公开(公告)号：US08423944B2

公开(公告)日：2013-04-16

申请号：US12640677

申请日：2009-12-17

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A design supporting method includes partitioning a partition path of circuit information into partitioned paths based on a given condition, calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corresponding partitioned path, calculating a partition propagation delay time of each of the partitioned paths based on the variation value of the corresponding partitioned path, and calculating a source propagation delay time of the source path by merging the propagation delay time of each of the partitioned paths.

摘要翻译： 一种设计支持方法，包括基于给定条件将电路信息的分割路径划分为分割路径，基于对应的分割路径中包含的单元的延迟的变化值，计算每个分割路径的变化值， 基于对应的分割路径的变化值，分割出各分割路径的分割传播延迟时间，并且通过合并每个分割路径的传播延迟时间来计算源路径的源传播延迟时间。

公开(公告)号：US20100318341A1

公开(公告)日：2010-12-16

申请号：US12792979

申请日：2010-06-03

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitance value.

摘要翻译： 非瞬时计算机可读记录介质中存储有使处理器执行输入集中常数电容值中包含的驱动能力值，集总常数电容值和输入电容值的程序，分别定义在 电路模型，并且基于驱动能力值和集总常数电容值进一步输入电路模型的第一延迟时间; 设置电路模型，驱动能力值，集总常数电容值和输入电容值; 通过向仿真器提供其中设置的值的电路模型，获取电路模型的第二延迟时间; 计算第一延迟时间和第二延迟时间的相对评估值; 将存储装置和延迟时间校正系数存储到与驱动能力值，集总常数电容值和输入电容值相关的相对评价值。

公开(公告)号：US08433022B2

公开(公告)日：2013-04-30

申请号：US13113461

申请日：2011-05-23

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04L7/002 ,  H04L7/041

摘要： A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.

摘要翻译： 时钟数据恢复电路包括：基于采样时钟接收输入数据的接收电路;将从接收电路输出的串行数据转换成并行数据的解复用器;时钟/数据恢复部件，其从并行数据输出端检测相位信息; 并且通过基于相位信息调整参考时钟的相位来生成采样时钟，执行从解复用器输出的并行数据的频率分析的数据模式分析器和检测时钟恢复状态的混叠检测器 基于并行数据频率的分析结果。

公开(公告)号：US20120039426A1

公开(公告)日：2012-02-16

申请号：US13113461

申请日：2011-05-23

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04L7/002 ,  H04L7/041

摘要： A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.

摘要翻译： 时钟数据恢复电路包括：基于采样时钟接收输入数据的接收电路;将从接收电路输出的串行数据转换成并行数据的解复用器;时钟/数据恢复部件，其从并行数据输出端检测相位信息; 并且通过基于相位信息调整参考时钟的相位来生成采样时钟，执行从解复用器输出的并行数据的频率分析的数据模式分析器和检测时钟恢复状态的混叠检测器 基于并行数据频率的分析结果。

公开(公告)号：US20060107150A1

公开(公告)日：2006-05-18

申请号：US11095662

申请日：2005-04-01

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： G01R31/28

CPC分类号： G01R31/31703

摘要： A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same configuration. To test these digital filters, comparison circuits comparing an output value and an expected value are individually provided per one digital filter. The digital filters and the comparison circuits are daisy-chained such that the output values of the first and second digital filters are inputted as the expected values of the comparison circuits corresponding to the second and third digital filters, respectively. When the same test signal is inputted to each digital filter from a built-in self test (BIST) controller, occurrence of abnormal circuits can be detected based on comparison results of the comparison circuits.

摘要翻译： 一种具有相同配置的多个电路的半导体器件，其中由于不需要与电路数量相对应的数量的期望值，因此在短时间内有效地执行操作测试。 该半导体器件具有相同配置的第一，第二和第三数字滤波器。 为了测试这些数字滤波器，每个数字滤波器分别提供比较输出值和期望值的比较电路。 数字滤波器和比较电路被菊花链式连接，使得第一和第二数字滤波器的输出值分别作为与第二和第三数字滤波器对应的比较电路的期望值输入。 当从内置的自检（BIST）控制器将相同的测试信号输入到每个数字滤波器时，可以基于比较电路的比较结果来检测异常电路的发生。