公开(公告)号：US4744063A

公开(公告)日：1988-05-10

申请号：US613614

申请日：1984-05-24

Applicant: Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

Inventor： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

IPC: G11C11/41 ,  G11C8/18 ,  G11C11/418 ,  G11C16/06 ,  G11C8/00

CPC classification number: G11C11/418 ,  G11C8/18

Abstract: A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.

Abstract translation: 静态存储器具有地址转换检测器，输入数据转换检测器和脉冲信号发生器。 当检测器检测到输入地址或输入数据已经改变时，脉冲信号发生器产生具有比数据读取或数据写入周期更短的宽度的脉冲信号。 该脉冲信号控制穿透DC电流通过存储器的一些部件在两个电源之间流动的时间段。

公开(公告)号：US5075886A

公开(公告)日：1991-12-24

申请号：US375856

申请日：1989-07-06

Applicant: Mitsuo Isobe ,  Hisashi Ueno

Inventor： Mitsuo Isobe ,  Hisashi Ueno

IPC: G11C7/00 ,  G11C11/403 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406

Abstract: A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level also changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

Abstract translation: 用于伪静态随机存取存储器的刷新控制电路包括刷新控制信号输出电路，用于输出刷新控制信号以完成伪静态随机存取存储器的刷新控制，并且包括延迟电路。 来自诸如MPU的控制装置的第一芯片使能信号被延迟电路延迟并作为PSRAM的第二芯片使能信号输出。 当第一芯片使能信号电平从选择电平变化到非选择电平时，刷新控制信号电平也变为非刷新电平。 该状态保持预定的时间。 在第二芯片使能信号从选择电平变化到非选择电平之后，刷新控制信号从非刷新电平返回到刷新电平。 因此，PSRAM在非选择状态期间进入刷新状态，并被刷新。 这种刷新操作必须在访问PSRAM之后执行。

公开(公告)号：US4982288A

公开(公告)日：1991-01-01

申请号：US310925

申请日：1989-02-16

Applicant: Mitsuo Isobe ,  Masanori Hamada

Inventor： Mitsuo Isobe ,  Masanori Hamada

IPC: H04N5/45 ,  H04N7/015

CPC classification number: H04N7/0152 ,  H04N5/45

Abstract: A television signal receiving apparatus of the type in which when performing a picture in picture operation by receiving a plurality of picture signals compressed in band width by multiple sub-Nyquist sampling, a sub-channel signal is first subjected to a spatial interpolating process and combined with a main-channel signal. The still picture portion and moving picture portion of a first input signal are restored to a field offset sub-sampled first picture signal, and a second input signal is restored to a field offset sub-sampled picture signal, subjected to a size-reducing process by time base compression in the vertical and horizontal directions of the picture and delivered as a second picture signal of the form synchronized in phase with a given position of the first picture signal. The first and second picture signals are time-division multiplexed to deliver a third picture signal onto a picture screen.

Abstract translation: 一种电视信号接收装置，其中当通过接收通过多次奈奎斯特采样以带宽压缩的多个图像信号执行图像操作时，首先对子信道信号进行空间内插处理并组合 具有主通道信号。 将第一输入信号的静止图像部分和运动图像部分恢复为场偏移次采样的第一图像信号，并且将第二输入信号恢复到经过尺寸减小处理的场偏移次采样图像信号 通过在图像的垂直和水平方向上的时基压缩，并作为与第一图像信号的给定位置同步的形式的第二图像信号而被输出。 第一和第二图像信号被时分复用以将第三图像信号传送到图像屏幕上。

公开(公告)号：US4891699A

公开(公告)日：1990-01-02

申请号：US314088

申请日：1989-02-23

Applicant: Masanori Hamada ,  Takeshi Inoue ,  Mitsuo Isobe ,  Yuichi Ninomiya ,  Yoshimichi Ohtsuka ,  Yoshinori Izumi

Inventor： Masanori Hamada ,  Takeshi Inoue ,  Mitsuo Isobe ,  Yuichi Ninomiya ,  Yoshimichi Ohtsuka ,  Yoshinori Izumi

IPC: H04N7/015 ,  H04N7/12

CPC classification number: H04N7/125 ,  H04N7/015

Abstract: When the receiving system for a band-compression image signal receives a dropout signal representing a dropout portion of an image signal, an output of the third delay circuit of the temporal filter for motion detection processing, that is, motion information of an image signal, which precedes by one field, and a dropout signal activate the signal selection control circuit to produce an output signal for controlling the operation of the signal selection circuit, so that an output signal of the first delay circuit is selected for a static portion of an image, and an output signal of the dropout compensation circuit is selected for a moving portion of an image, so as to effect compensation control of the dropout portion of an image signal, thereby preventing deterioration of the quality of an image.

Abstract translation: 当带式压缩图像信号的接收系统接收到表示图像信号的压差部分的压差信号时，用于运动检测处理的时间滤波器的第三延迟电路的输出，即图像信号的运动信息， 其前置一个场，并且一个丢失信号激活信号选择控制电路以产生用于控制信号选择电路的操作的输出信号，使得第一延迟电路的输出信号被选择用于图像的静态部分 ，并且为图像的运动部分选择压差补偿电路的输出信号，以便实现图像信号的压差部分的补偿控制，从而防止图像质量的劣化。

公开(公告)号：US4882708A

公开(公告)日：1989-11-21

申请号：US145411

申请日：1988-01-19

Applicant: Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

Inventor： Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

IPC: G11C11/41 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A precharge circuit is provided between bit lines, on the one hand, and a power source potential on the other. The precharge circuit is controlled to be conductive/nonconductive by a clear signal. A control unit is also provided, which controls a decoder when the clear signal is supplied so as to set all the word lines in a selective state. In a clear mode, writing circuits write the same data simultaneously into all of the memory cells.

Abstract translation: 一方面，位线之间和另一方的电源电位之间设置预充电电路。 通过清除信号将预充电电路控制为导通/不导通。 还提供控制单元，当提供清除信号时，控制解码器，以将所有字线设置为选择状态。 在清除模式下，写入电路将同一数据同时写入所有存储单元。

公开(公告)号：US4833652A

公开(公告)日：1989-05-23

申请号：US171860

申请日：1988-03-22

Applicant: Mitsuo Isobe ,  Tohru Kimura

Inventor： Mitsuo Isobe ,  Tohru Kimura

IPC: G06F11/00 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C29/72 ,  G06F11/076 ,  G11C29/44

Abstract: A defect detection circuit for detecting a defect of a memory cell, a counter for counting defects detected by the defect detect circuit, and a remediableness determination unit for determining whether a count of the counter allows remedy by a redundancy circuit, are provided in a tester for a semiconductor memory or on a memory chip having a redundancy circuit. When the count of the counter is the same as or smaller than the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory is determined to be "remediable." Otherwise, the memory is determined to be "unremediable." When the count of the counter exceeds the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory test is interrupted.

Abstract translation: 用于检测存储单元的缺陷的缺陷检测电路，用于对由缺陷检测电路检测的缺陷进行计数的计数器以及用于确定计数器的计数是否允许通过冗余电路进行补救的补偿性确定单元设置在测试器中 用于半导体存储器或具有冗余电路的存储器芯片。 当计数器的计数等于或小于冗余电路的辅助行和列中的至少一个的数量时，确定存储器是“可补救的”。 否则，内存被确定为“不可重新”。 当计数器的计数超过冗余电路的至少一个辅助行和列的数量时，存储器测试被中断。

公开(公告)号：US4587638A

公开(公告)日：1986-05-06

申请号：US630115

申请日：1984-07-12

Applicant: Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

Inventor： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

IPC: G11C29/00 ,  G11C7/02

CPC classification number: G11C29/84 ,  G11C29/832

Abstract: In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

Abstract translation: 在根据本发明的半导体存储器件中，当存储单元中存在缺陷部分时，这些存储单元被冗余存储单元替换。 当在存储单元中发现有缺陷的部分时，与具有缺陷部分的存储单元相对应的熔丝元件被切断。 连接到具有缺陷部分的存储单元的选择线的电压由电阻器保持在L电平。 因此，不选择具有缺陷部分的存储单元。

公开(公告)号：US4563593A

公开(公告)日：1986-01-07

申请号：US538277

申请日：1983-10-03

Applicant: Mitsuo Isobe ,  Takayuki Ohtani

Inventor： Mitsuo Isobe ,  Takayuki Ohtani

IPC: H03K5/1532 ,  H03K3/02 ,  H03K5/1534 ,  H03K5/153

CPC classification number: H03K5/1534 ,  H03K3/02

Abstract: A transition detector circuit comprises a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal, a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to the signal input terminal, while the output thereof is connected to an antiphase output terminal, a third invertor train comprising at least one stage of an invertor, which is connected to the output of the first invertor train, a fourth invertor train, comprising at least one stage of an invertor, which is connected to the output of the second invertor train, and a fifth invertor train comprising at least one stage of an invertor, which is connected to the signal input terminal. The transition detector circuit further comprises a first switching circuit which turns on or off in response to a signal fed from the third invertor train to produce a pulse signal having a first delay time determined by the first and third invertor trains, and a second switching circuit which turns on or off in response to a signal fed from the fourth invertor train and turns off or on in response to a signal fed from the fifth invertor train to produce a pulse signal having a second delay time determined by the second, fourth and fifth invertor trains.

Abstract translation: 一个转换检测器电路包括一个包括2n级反相器（n：包括零的正整数）的第一个反相器列，其输入连接到一个信号输入端，同时其输出连接到一个同相输出端，一个第二反相器 其包括2n + 1级的反相器，其输入连接到信号输入端，而其输出连接到反相输出端，第三反相器列，包括至少一级的反相器，其连接到反相器 第一反相器列车的输出，第四反相器列车，包括连接到第二逆变器列车的输出端的反相器的至少一级，以及包括连接到第二逆变器列的至少一级的逆变器列 到信号输入端子。 转换检测器电路还包括第一开关电路，其响应于从第三反相器序列馈送的信号而导通或截止以产生具有由第一和第三反相器列车确定的第一延迟时间的脉冲信号，以及第二开关电路 其响应于从第四反相器列车馈送的信号而接通或断开，并且响应于从第五反相器列车馈送的信号而断开或接通，以产生具有由第二，第四和第五变换器确定的第二延迟时间的脉冲信号 倒车火车

公开(公告)号：US4524389A

公开(公告)日：1985-06-18

申请号：US438466

申请日：1982-11-02

Applicant: Mitsuo Isobe ,  Tetsuo Kutsuki ,  Namio Yamaguchi ,  Toshihide Tanaka

Inventor： Mitsuo Isobe ,  Tetsuo Kutsuki ,  Namio Yamaguchi ,  Toshihide Tanaka

IPC: H03B5/12 ,  H04N5/21 ,  H04N5/455 ,  H04N5/44 ,  H04B1/68

CPC classification number: H04N5/455 ,  H03B5/1209 ,  H03B5/1231 ,  H04N5/21

Abstract: In a synchronous video detector circuit using a phase-locked loop, the synchronous detection of a video IF signal is effected with a synchronous carrier signal reproduced by the PLL including a voltage-controlled oscillator. Each of a phase comparator of the PLL and a synchronous video detector has its input terminal connected to an output terminal of a video IF amplifier by untuned coupling, and arranged on the output side of the synchronous video detector is a phase-locked mode detector for detecting that the PLL is in its phase-locked mode. The phase-locked mode detector is adapted to control the band width of a low-pass filter of the PLL in either a narrow band mode or a wide band mode and the low-pass filter is controlled to operate in the narrow band mode only when the PLL is in the phase-locked mode of operation. The black and white noise included in the output signal of the synchronous video detector are both cancelled by a noise cancellation circuit including a black noise detector for pulse noise cancellation purposes.

Abstract translation: 在使用锁相环的同步视频检测器电路中，视频IF信号的同步检测由包括压控振荡器的PLL再现的同步载波信号来实现。 PLL的相位比较器和同步视频检测器中的每一个都具有通过非连续耦合连接到视频IF放大器的输出端的输入端，并且在同步视频检测器的输出侧布置有锁相模式检测器 检测到PLL处于其锁相模式。 锁相模式检测器适于在窄带模式或宽带模式中控制PLL的低通滤波器的带宽，并且低通滤波器被控制为仅在窄带模式下操作， PLL处于锁相操作模式。 包括在同步视频检测器的输出信号中的黑白噪声都被包括用于脉冲噪声消除目的的黑噪声检测器的噪声消除电路消除。

公开(公告)号：US4360929A

公开(公告)日：1982-11-23

申请号：US160325

申请日：1980-06-17

Applicant: Mitsuo Isobe

Inventor： Mitsuo Isobe

IPC: H03G3/20 ,  H03G3/34 ,  H04N5/52

CPC classification number: H03G3/3052 ,  H03G3/3068 ,  H03G3/34 ,  H04N5/52

Abstract: An AGC circuit includes an amplitude synchronous detector using a phase-locked loop (PLL), a variable gain amplifier for supplying a signal to this detector, and a means for controlling the amplification degree of the amplifier to make the output signal level constant. More specifically, the AGC circuit includes a first AGC loop including an AGC detector and a low-pass filter provided before the AGC detector, a second AGC loop including a synchronous detector and a phase synchronized state detecting circuit DC coupled to the output end of the synchronous detector, the output signal from the phase synchronized state detecting circuit being used to control the AGC circuit, and a noise eliminating circuit provided at the final stage for adding the output signal from the phase synchronized state detecting circuit and the output signal from the synchronous detector, or for performing subtraction between both the signals.

Abstract translation: AGC电路包括使用锁相环（PLL）的振幅同步检测器，用于向该检测器提供信号的可变增益放大器，以及用于控制放大器的放大度以使输出信号电平恒定的装置。 更具体地说，AGC电路包括第一AGC环路，其包括AGC检测器和在AGC检测器之前提供的低通滤波器，第二AGC环路，包括同步检测器和相位同步状态检测电路DC，耦合到该输出端的输出端 来自相位同步状态检测电路的输出信号用于控制AGC电路，以及设置在最后级的噪声消除电路，用于将来自相位同步状态检测电路的输出信号和来自同步状态检测电路的输出信号相加 检测器，或用于在两个信号之间进行减法。