Abstract:
A transistor circuit having a plurality of constant current sources wherein a compensating resistor of a predetermined value is inserted between the base of the transistor of one of the constant current sources and a reference voltage supply terminal. The compensating resistor serves to equalize the current variation between currents flowing through first and second resistive loads and thereby equalizes D.C. circuit output potentials for the circuits being driven by the constant current sources. This equalization is achieved irrespective of variations in transistor current gain due to temperature fluctuation or manufacturing error.
Abstract:
A variable gain amplifier has a first amplifier circuit whose gain is A/n times (A being a real number excepting "0", and n being a real number larger than 1); a second amplifier circuit whose gain is A(n-1/n) times; level converter for level converting an output signal from the second amplifier circuit at a ratio corresponding to a level of a gain control signal having a predetermined level controllable range and at a ratio of 1/(n+1) at a central level within the level controllable range of the gain control signal; and an adder circuit for adding together an output signal from the level converter and an output signal from the first amplifier circuit at the ratio of 1:1. The variable gain amplifier has a gain controllable range of among 1/n.about.1.about.n times as the level of the gain control signal changes among the minimum level.about.the central level.about.the maximum level. When the gain of the second amplifier circuit is set to A(m-1/n) times (m being a real number larger than 1) and a level conversion ratio of the level converter is set to (1-1/n)/(m-1/n) at the central level of the gain control signal, the variable gain amplifer having the gain controllable range of among A/n.about.A.about.mA times is realized.
Abstract:
A trigger pulse generator circuit for converting an input pulse into a sharp pulse to be used as a trigger pulse is disclosed. The input pulse is applied to a first and a second switching means which are connected in cascade, the second switching means having a larger delay time than that of the first switching means. An output trigger pulse is derived from a connecting point of the first and second switching means. The first switching means becomes cut-off in response to the removal of the input pulse, while the second switching means becomes cut-off a predetermined time after the removal of the input pulse due to a time delay caused by the storage time of a transistor of the second switching means. In consequence, a sharp trigger pulse is derived from the output terminal. Preferably, a discharging means for the charge stored in the second switching means is further provided between the ground and the second switching means. This trigger pulse generator circuit is advantageous in that no capacitive element is necessitated, and so it is quite suitable for application to an integrated circuit.