公开(公告)号：US20100177422A1

公开(公告)日：2010-07-15

申请号：US12351747

申请日：2009-01-09

Applicant: Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

Inventor： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

IPC: G11B5/09 ,  G11B5/78

CPC classification number: G11B20/1833 ,  G11B20/1201 ,  G11B20/1866 ,  G11B2020/1287 ,  G11B2020/1289 ,  G11B2020/1446 ,  G11B2020/1836 ,  G11B2220/93 ,  H03M13/27 ,  H03M13/271

Abstract: For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1−K1 C1-parity bytes are generated for each row and N2−K2 C2-parity bytes are generated for each column. The C1 and C2 parity bytes are appended to the ends of the row and column, respectively, to form encoded C1 and C2 codewords, respectively. All of the C1 codewords per data set are endowed with a specific codeword header to form a plurality of partial codeword objects (PCOs). Each PCO is mapped onto a logical data track according to information within the header. On each logical data track, adjacent PCOs are merged to form COs which are modulation encoded and mapped into synchronized COs. Then T synchronized COs are written simultaneously to the data tape where T is the number of concurrent active tracks on the data tape.

Abstract translation: 为了将数据写入多轨磁带，接收到的数据集并被分割成未编码的子数据集，每个子​​集包括具有K2行和K1列的阵列。 对于每个未编码的子数据集，为每行生成N1-K1 C1-奇偶校验字节，并为每列生成N2-K2 C2-奇偶校验字节。 C1和C2奇偶校验字节分别附加到行和列的末端，分别形成编码的C1和C2码字。 每个数据集的所有C1码字都具有特定的码字头以形成多个部分码字对象（PCO）。 每个PCO根据标题内的信息被映射到逻辑数据轨道上。 在每个逻辑数据轨道上，相邻的PCO被合并以形成被调制编码并被映射到同步的CO中的CO。 然后将T同步的CO同时写入数据磁带，其中T是数据磁带上的并发活动磁道的数量。

公开(公告)号：US20080209420A1

公开(公告)日：2008-08-28

申请号：US12039412

申请日：2008-02-28

Applicant: Hisato Matsuo

Inventor： Hisato Matsuo

IPC: G06F9/46

CPC classification number: G06F3/0656 ,  G06F3/0613 ,  G06F3/0682

Abstract: Provided is a technology capable of managing the processing status of hardware blocks by a less number of registers. A processing system includes a buffer composed of a plurality of segments which store data, which is to be input to the processing system, in transactions in the order of inputting, respectively; a plurality of processing units which perform a series of processes in a given order for the data; a plurality of first tables corresponding to the plurality of processing units, respectively, the first tables each storing beginning information which indicates a beginning segment among a plurality of segments at continuous addresses completed in the process by the corresponding processing unit, end information which indicates an end segment among them, and existence information which indicates the presence or absence of segments completed in the process by the corresponding processing unit; and a management unit which manages a data transfer between the buffer and the plurality of processing units so that the series of processes are performed in a given order on the basis of the processing status of the series of processes retained in the plurality of first tables.

Abstract translation: 提供了能够通过较少数量的寄存器来管理硬件块的处理状态的技术。 一种处理系统，包括分别以输入顺序存储要输入到处理系统的数据的多个段的缓冲器; 多个处理单元，以给定顺序执行数据的一系列处理; 分别对应于多个处理单元的多个第一表，每个存储开始信息的第一表，其中表示在相应处理单元处理完成的连续地址的多个段中的起始段，表示一个 以及存在信息，其指示由对应的处理单元在该处理中完成的段的存在或不存在; 以及管理单元，其管理所述缓冲器和所述多个处理单元之间的数据传送，使得根据保持在所述多个第一表中的所述一系列处理的处理状态，以给定的顺序执行所述一系列处理。

公开(公告)号：US08762805B2

公开(公告)日：2014-06-24

申请号：US12957651

申请日：2010-12-01

Applicant: Roy Daron Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J Seger ,  Keisuke Tanaka

Inventor： Roy Daron Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J Seger ,  Keisuke Tanaka

IPC: G06F11/00

CPC classification number: G06F11/1012 ,  H03M13/1515 ,  H03M13/2909

Abstract: A method for decoding encoded data comprising integrated data and header protection is disclosed herein. In one embodiment, such a method includes receiving an extended data array. The extended data array includes a data array organized into rows and columns, headers appended to the rows of the data array, column ECC parity protecting the columns of the data array, and row ECC parity protecting the rows and headers combined. The method then decodes the extended data array. Among other operations, this decoding step includes checking the header associated with each row to determine whether the header is legal. If the header is legal, the method determines the contribution of the header to the corresponding row ECC parity. The method then reverses the contribution of the header to the corresponding row ECC parity. A corresponding apparatus (i.e., a tape drive configured to implement the above-described method) is also disclosed herein.

Abstract translation: 本文公开了一种用于对包括集成数据和报头保护的编码数据进行解码的方法。 在一个实施例中，这种方法包括接收扩展数据阵列。 扩展数据阵列包括组织成行和列的数据阵列，附加到数据阵列行的标题，保护数据阵列列的ECC ECC奇偶校验和保护行和头组合的行ECC奇偶校验。 该方法然后解码扩展数据数组。 在其他操作中，该解码步骤包括检查与每行关联的标题以确定标题是否合法。 如果标题是合法的，则该方法确定标题对相应行ECC奇偶校验的贡献。 该方法然后将标题的贡献反转到对应的行ECC奇偶校验。 本文还公开了相应的装置（即，被配置为实现上述方法的磁带驱动器）。

公开(公告)号：US08645800B2

公开(公告)日：2014-02-04

申请号：US13451233

申请日：2012-04-19

Applicant: Roy Daron Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J Seger ,  Keisuke Tanaka

Inventor： Roy Daron Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J Seger ,  Keisuke Tanaka

IPC: G06F11/00

CPC classification number: G11B20/18 ,  G11B2020/184 ,  G11B2020/1853 ,  G11B2220/90

Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.

Abstract translation: 在磁带驱动器中集成数据和头部保护的方法包括接收一组数据组织成行和列。 该数组被扩展以包括数组中每行数据的一个或多个头。 该方法为阵列中的数据提供了二维纠错码（ECC）保护，并为阵列中的标头提供了ECC保护的一个维度。 本文还公开了相应的装置。

公开(公告)号：US20130179645A1

公开(公告)日：2013-07-11

申请号：US13344941

申请日：2012-01-06

Applicant: Hisato Matsuo ,  Rika Nagahara ,  Scott J. Schaffer

Inventor： Hisato Matsuo ,  Rika Nagahara ,  Scott J. Schaffer

IPC: G06F12/00

CPC classification number: G06F9/544 ,  G06F12/00 ,  G06F15/167

Abstract: A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

Abstract translation: 公开了一种使用共享存储器系统来均衡使用者带宽的方法。 在一个实施例中，这种方法包括接收访问共享存储器系统的多个访问请求。 每个访问请求源自耦合到共享存储器系统的不同请求者。 该方法然后确定哪个访问请求已经等待最长时间访问共享存储器系统。 然后对访问请求进行排序，使得等待最长的访问请求在其他访问请求之后被传送到共享存储器系统。 与最长等待的访问请求相关联的请求者然后可以在发送最长等待的访问请求之后立即向附加存储器系统发送附加访问请求。 还公开了相应的装置和计算机程序产品。

公开(公告)号：US08484412B2

公开(公告)日：2013-07-09

申请号：US12613259

申请日：2009-11-05

Applicant: Allen Keith Bates ,  Steven Ross Bentley ,  Randall Scot Doan ,  Katsuhiko Hagiwara ,  Fahnmusa Christian Jangaba ,  Christine Renee Knibloe ,  Hisato Matsuo ,  Hirokazu Nakayama ,  Mitsuhiro Nishida ,  Daniel James Winarski

Inventor： Allen Keith Bates ,  Steven Ross Bentley ,  Randall Scot Doan ,  Katsuhiko Hagiwara ,  Fahnmusa Christian Jangaba ,  Christine Renee Knibloe ,  Hisato Matsuo ,  Hirokazu Nakayama ,  Mitsuhiro Nishida ,  Daniel James Winarski

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G11B15/026

Abstract: A magnetic tape drive having a tape drive system for moving magnetic tape, tape read/write and servo system, tape cartridge load/unload systems, I/O communications, memory; and a control system, operates in three modes to conserve energy consumption. A first low power mode powers the I/O communications, the memory, and the control system. If a magnetic tape cartridge is in loaded position in the magnetic tape drive, the second low power mode powers the same as the first low power mode, and additionally powers the tape drive system to apply tension to a magnetic tape of the magnetic tape cartridge. In the first and the second low power modes, the control system operates the I/O communications, the memory and the control system to respond to and execute commands received at the I/O communications if the commands are executable without magnetic tape access. The third, full power mode, is entered if a command received at the I/O communications requires magnetic tape access.

Abstract translation: 一种磁带驱动器，具有用于移动磁带，磁带读/写和伺服系统的磁带驱动系统，磁带盒装载/卸载系统，I / O通信，存储器; 和控制系统，以三种模式运行，以节省能源消耗。 第一个低功耗模式为I / O通信，存储器和控制系统供电。 如果磁带驱动器中的磁带盒处于装载位置，则第二低功率模式与第一低功率模式相同，并且另外为磁带驱动系统供电以向磁带盒的磁带施加张力。 在第一和第二低功率模式中，如果命令可执行而没有磁带存取，则控制系统操作I / O通信，存储器和控制系统来响应并执行在I / O通信中接收的命令。 如果在I / O通信中接收的命令需要磁带访问，则输入第三个全功率模式。

公开(公告)号：US20120144271A1

公开(公告)日：2012-06-07

申请号：US12957651

申请日：2010-12-01

Applicant: Roy D. Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J. Seger ,  Keisuke Tanaka

Inventor： Roy D. Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J. Seger ,  Keisuke Tanaka

IPC: G11C29/00

CPC classification number: G06F11/1012 ,  H03M13/1515 ,  H03M13/2909

Abstract: A method for decoding encoded data comprising integrated data and header protection is disclosed herein. In one embodiment, such a method includes receiving an extended data array. The extended data array includes a data array organized into rows and columns, headers appended to the rows of the data array, column ECC parity protecting the columns of the data array, and row ECC parity protecting the rows and headers combined. The method then decodes the extended data array. Among other operations, this decoding step includes checking the header associated with each row to determine whether the header is legal. If the header is legal, the method determines the contribution of the header to the corresponding row ECC parity. The method then reverses the contribution of the header to the corresponding row ECC parity. A corresponding apparatus (i.e., a tape drive configured to implement the above-described method) is also disclosed herein.

Abstract translation: 本文公开了一种用于对包括集成数据和报头保护的编码数据进行解码的方法。 在一个实施例中，这种方法包括接收扩展数据阵列。 扩展数据阵列包括组织成行和列的数据阵列，附加到数据阵列行的标题，保护数据阵列列的ECC ECC奇偶校验和保护行和头组合的行ECC奇偶校验。 该方法然后解码扩展数据数组。 在其他操作中，该解码步骤包括检查与每行关联的标题以确定标题是否合法。 如果标题是合法的，则该方法确定标题对相应行ECC奇偶校验的贡献。 该方法然后将标题的贡献反转到对应的行ECC奇偶校验。 本文还公开了相应的装置（即，被配置为实现上述方法的磁带驱动器）。

公开(公告)号：US07987404B2

公开(公告)日：2011-07-26

申请号：US11721446

申请日：2005-12-21

Applicant: Junichi Fukuda ,  Hisato Matsuo

Inventor： Junichi Fukuda ,  Hisato Matsuo

IPC: H03M13/00

CPC classification number: G11B20/1803 ,  G11B20/1833 ,  G11B2020/10629 ,  G11B2020/1823 ,  G11B2020/1853 ,  G11B2220/90

Abstract: A method for transferring corrected data to an external buffer within a tape drive is provided. After the receipt of data from a data recording medium, the data are stored in an external buffer. The data are then transferred from the external buffer to an error correction code (ECC) device. Any error in the data within the ECC device are corrected. The corrected data are subsequently divided into multiple sub-units, and a transfer flag is added to each of the sub-units having corrected data. Only the sub-units having corrected data are transferred from the ECC device back to the external buffer.

Abstract translation: 提供了一种用于将校正数据传送到磁带机内的外部缓冲器的方法。 在从数据记录介质接收数据之后，将数据存储在外部缓冲器中。 然后将数据从外部缓冲器传送到纠错码（ECC）设备。 纠正ECC设备内的数据错误。 校正后的数据随后被分成多个子单元，并将传送标志加到具有校正数据的每个子单元中。 只有具有校正数据的子单元才从ECC设备传送回外部缓冲器。

公开(公告)号：US07965462B2

公开(公告)日：2011-06-21

申请号：US12351725

申请日：2009-01-09

Applicant: Masayuki Demura ,  Glen A. Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

Inventor： Masayuki Demura ,  Glen A. Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

IPC: G11B20/16

CPC classification number: G11B20/1201 ,  G11B20/18 ,  G11B20/1866 ,  G11B2020/1222 ,  G11B2220/90 ,  H03M13/271 ,  H03M13/2909

Abstract: Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

Abstract translation: 方法，逻辑，设备和计算机程序产品写入数据，包括少于一个完整的数据集，到磁带。 从主机接收数据，发出不交错命令，并计算C1和C2 ECC。 然后形成Codeword Quad（CQ）集合。 将数据集的至少一个CQ集以非交错方式写入磁带，并且数据集信息表（DSIT）被写入紧跟在至少一个写入的CQ集之后的磁带上。 可以使用地址变换来取消交织。 编写CQ集可以包括将CQ集的多个连续实例写入磁带以保持ECC能力的有效性。

公开(公告)号：US09268721B2

公开(公告)日：2016-02-23

申请号：US13989743

申请日：2011-10-06

Applicant: Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

Inventor： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/16

CPC classification number: G11C7/1048 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1663 ,  G06F13/4234 ,  G11C7/1072

Abstract: The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

Abstract translation: 本发明包括使用存储器作为主存储器的多个CPU，使用存储器作为缓冲器的另一功能块，控制从多个CPU到存储器的访问传输的CPU接口，以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中，CPU接口使得来自多个CPU的访问请求等待，并且接收并存储每个访问的地址，数据传输模式和数据大小，向DRAM控制器通知访问请求，然后在接收到 访问请求根据授权信号向DRAM控制器发送信息，于是DRAM控制器接收授权信号，并且基于访问仲裁，指定已经被授权传输的CPU，以便将授权信号发送到 CPU接口。